TMS320DM6467 Datasheet, PDF (258/334 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403 – DECEMBER 2007
www.ti.com
HEX ADDRESS
RANGE
0x01C6 41B4
0x01C6 41B8
0x01C6 41BC
0x01C6 41C0
0x01C6 41C4
0x01C6 41C8
0x01C6 41CC
0x01C6 41D0
0x01C6 41D4
0x01C6 41D8
0x01C6 41DC
0x01C6 41E0
0x01C6 41E4
0x01C6 41E8
0x01C6 41EC
0x01C6 41F0
0x01C6 41F4
0x01C6 41F8
0x01C6 41FC
0x01C6 4200 -
0x01C6 43FF
0x01C6 4400
0x01C6 4401
0x01C6 4402
0x01C6 4404
0x01C6 4406
0x01C6 4408
0x01C6 440A
0x01C6 440B
0x01C6 440C
0x01C6 440E
0x01C6 440F
0x01C6 4410
0x01C6 4412
0x01C6 4414
Table 6-75. USB 2.0 Registers (continued)
ACRONYM
REGISTER NAME
RCPPIDMASTATEW5
RX CPPI DMA State Word 5
RCPPIDMASTATEW6
RX CPPI DMA State Word 6
RCPPICOMPPTR
RX CPPI Completion Pointer
TX/RX CCPI Channel 3 State Block
TCPPIDMASTATEW0
TX CPPI DMA State Word 0
TCPPIDMASTATEW1
TX CPPI DMA State Word 1
TCPPIDMASTATEW2
TX CPPI DMA State Word 2
TCPPIDMASTATEW3
TX CPPI DMA State Word 3
TCPPIDMASTATEW4
TX CPPI DMA State Word 4
TCPPIDMASTATEW5
TX CPPI DMA State Word 5
–
Rserved
TCPPICOMPPTR
TX CPPI Completion Pointer
RCPPIDMASTATEW0
RX CPPI DMA State Word 0
RCPPIDMASTATEW1
RX CPPI DMA State Word 1
RCPPIDMASTATEW2
RX CPPI DMA State Word 2
RCPPIDMASTATEW3
RX CPPI DMA State Word 3
RCPPIDMASTATEW4
RX CPPI DMA State Word 4
RCPPIDMASTATEW5
RX CPPI DMA State Word 5
RCPPIDMASTATEW6
RX CPPI DMA State Word 6
RCPPICOMPPTR
RX CPPI Completion Pointer
–
Reserved
FADDR
POWER
INTRTX
INTRRX
INTRTXE
INTRRXE
INTRUSB
INTRUSBE
FRAME
INDEX
TESTMODE
TXMAXP
PERI_CSR0
HOST_CSR0
PERI_TXCSR
HOST_TXCSR
RXMAXP
Core Registers
Function Address Register
Power Management Register
Interrupt Register for Endpoint 0 plus TX Endpoints 1 to 4
Interrupt Register for RX Endpoints 1 to 4
Interrupt Enable Register for INTRTX
Interrupt Enable Register for INTRRX
Interrupt Register for Common USB Interrupts
Interrupt Enable Register for INTRUSB
Frame Number Register
Index register for selecting the endpoint status and control registers
Register to enable the USB 2.0 test modes
Maximum packet size for peripheral/host TX endpoint (Index register set to select
Endpoints 1 - 4 only)
Control Status register for Endpoint 0 in Peripheral mode. (Index register set to
select Endpoint 0)
Control Status register for Endpoint 0 in Host mode. (Index register set to select
Endpoint 0)
Control Status register for peripheral TX endpoint. (Index register set to select
Endpoints 1 - 4)
Control Status register for host TX endpoint. (Index register set to select
Endpoints 1 - 4)
Maximum packet size for peripheral/host RX endpoint (Index register set to select
Endpoints 1 - 4 only)
258 Peripheral Information and Electrical Specifications
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