TMS320DM6467 Datasheet, PDF (1/334 Pages) Texas Instruments – Digital Media System-on-Chip

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1 Digital Media System-on-Chip (DMSoC)
1.1 Features
• High-Performance Digital Media SoC
– 594-MHz C64x+™ Clock Rate
– 297-MHz ARM926EJ-S™ Clock Rate
– Eight 32-Bit C64x+ Instructions/Cycle
– 4752 C64x+ MIPS
– Fully Software-Compatible With C64x /
ARM9™
• Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
– Eight Highly Independent Functional Units
• Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
• Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
– Load-Store Architecture With Non-Aligned
Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Additional C64x+™ Enhancements
• Protected Mode Operation
• Exceptions Support for Error Detection
and Program Redirection
• Hardware Support for Modulo Loop
Operation
• C64x+ Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
– Additional Instructions to Support Complex
Multiplies
• C64x+ L1/L2 Memory Architecture
– 32K-Byte L1P Program RAM/Cache (Direct
Mapped)
– 32K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
– 128K-Byte L2 Unified Mapped RAM/Cache
(Flexible RAM/Cache Allocation)
TMS320DM6467
Digital Media System-on-Chip
SPRS403 – DECEMBER 2007
• ARM926EJ-S Core
– Support for 32-Bit and 16-Bit (Thumb®
Mode) Instruction Sets
– DSP Instruction Extensions and Single
Cycle MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ Logic for Real-Time
Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 8K-Byte Data Cache
– 32K-Byte RAM
– 8K-Byte ROM
• Embedded Trace Buffer™ (ETB11™) With 4KB
Memory for ARM9 Debug
• Endianness: Little Endian for ARM and DSP
• Dual Programmable High-Definition Video
Image Co-Processor (HDVICP) Engines
– Supports a Range of Encode, Decode, and
Transcode Operations
• H.264, MPEG2, VC1, MPEG4 SP/ASP
• Video Port Interface (VPIF)
– Two 8-Bit SD (BT.656), Single 16-Bit HD
(BT.1120), or Single Raw (8-/10-/12-Bit)
Video Capture Channels
– Two 8-Bit SD (BT.656) or Single 16-Bit HD
(BT.1120) Video Display Channels
• Video Data Conversion Engine (VDCE)
– Horizontal and Vertical Downscaling
– Chroma Conversion (4:2:2↔4:2:0)
• Two Transport Stream Interface (TSIF)
Modules
(One Parallel/Serial and One Serial Only)
– TSIF for MPEG Transport Stream
– Simultaneous Synchronous or
Asynchronous Input/Output Streams
– Absolute Time Stamp Detection
– PID Filter With 7 PID Filter Tables
– Corresponding Clock Reference Generator
(CRGEN) Modules for System Time-Clock
Recovery
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