TMS320DM6467 Datasheet, PDF (314/334 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403 – DECEMBER 2007
www.ti.com
Table 6-115. UART2 – UART/IrDA/CIR Register Program Map
HEX ADDRESS
RANGE
0x01C2 0800
0x01C2 0804
0x01C2 0808
0x01C2 080C
0x01C2 0810
0x01C2 0814
0x01C2 0818
0x01C2 081C
0x01C2 0820
0x01C2 0824
0x01C2 0828
0x01C2 082C
0x01C2 0830
0x01C2 0834
0x01C2 0838
0x01C2 083C
0x01C2 0840
0x01C2 0844
0x01C2 0848
0x01C2 084C
0x01C2 0850
0x01C2 0854
0x01C2 0858
0x01C2 085C
0x01C2 0860
0x01C2 0864 -
0x01C2 087F
LCR[7] = 0
READ
WRITE
RHR
IER ⁽¹⁾
IIR
THR
IER ⁽¹⁾
FCR ⁽²⁾
LCR
MCR ⁽²⁾
LCR
MCR ⁽²⁾
LSR
MSR/TCR ⁽³⁾
SPR/TLR ⁽³⁾
–
TCR ⁽³⁾
SPR/TLR ⁽³⁾
MDR1
MDR1
MDR2
MDR2
SFLSR
TXFLL
RESUME
TXFLH
SFREGL
RXFLL
SFREGH
RXFLH
BLR
BLR
ACREG
ACREG
SCR
SCR
SSR
–
EBLR
EBLR
–
–
MVR
–
SYSC
SYSC
SYSS
–
WER
WER
CFPS
CFPS
–
–
REGISTER
LCR[7] = 1 & LCR[7:0] ≠ 0xBF
READ
WRITE
DLL
DLL
DLH
IIR
DLH
FCR ⁽²⁾
LCR
MCR ⁽²⁾
LCR
MCR ⁽²⁾
LSR
MSR/TCR ⁽³⁾
SPR/TLR ⁽³⁾
–
TCR ⁽³⁾
SPR/TLR ⁽³⁾
MDR1
MDR1
MDR2
MDR2
SFLSR
TXFLL
RESUME
TXFLH
SFREGL
RXFLL
SFREGH
RXFLH
UASR
–
–
–
SCR
SCR
SSR
–
–
–
–
–
MVR
–
SYSC
SYSC
SYSS
–
WER
WER
CFPS
CFPS
–
–
LCR[7:0] = 0xBF
READ
WRITE
DLL
DLL
DLH
DLH
EFR
EFR
LCR
LCR
XON1/ADDR1
XON1/ADDR1
XON2/ADR2
XOFF1/TCR ⁽³⁾
XOFF2/TLR ⁽³⁾
XON2/ADDR2
XOFF1/TCR ⁽³⁾
XOFF2/TLR ⁽³⁾
MDR1
MDR1
MDR2
MDR2
SFLSR
TXFLL
RESUME
TXFLH
SFREGL
RXFLL
SFREGH
RXFLH
UASR
–
–
–
SCR
SCR
SSR
–
–
–
–
–
MVR
–
SYSC
SYSC
SYSS
–
WER
WER
CFPS
CFPS
–
–
(1) In UART modes, IER.[7:4] can only be written when ENHANCED_EN in EFR = 1. In IrDA/CIR modes, ENHANCED_EN in EFR has no
impact on the access to IER.[7:4].
(2) MCR.[7:5] and the TX_FIFO_TRIG bits in FCR can only be written to when the ENHANCED_EN bit in EFR = 1.
(3) Transmission control register (TCR) and trigger level register (TLR) are accessible only when the ENHANCED_EN bit in the EFR =1
and the TCR_TLR bit in the MCR = 1.
314 Peripheral Information and Electrical Specifications
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