TMS320DM6467 Datasheet, PDF (134/334 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403 – DECEMBER 2007
5.2 Recommended Operating Conditions
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CV_DD
DV_DD
V_SS
DDR_VREF
DDR_ZP
DDR_ZN
Supply voltage, Core (CV_DD, DEV_CV_DD, AUX_CV_DD) ⁽¹⁾
Supply voltage, I/O, 3.3V (DV_DD33, USB_V_DDA3P3)
Supply voltage, I/O, 1.8V (DV_DDR2, PLL1V_DD18, PLL2V_DD18,
DEV_DV_DD18, AUX_DV_DD18, USB_V_DD1P8(2))
Supply ground (V_SS, PLL1V_SS, PLL2V_SS, DEV_V_SS(3),
AUX_V_SS(3), USB_V_SSREF)
DDR2 reference voltage⁽⁴⁾
DDR2 impedance control, connected via 48.7-Ω (±0.5%
tolerance) resistor to V_SS
DDR2 impedance control, connected via 48.7-Ω (±0.5%
tolerance) resistor to DV_DDR2
High-level input voltage, 3.3 V (except PCI-capable and I2C
pins)
MIN
1.14
3.14
1.71
0
0.49DV_DDR2
2
NOM
1.2
3.3
1.8
0
0.5DV_DDR2
V_SS
DV_DDR2
MAX UNIT
1.26 V
3.46 V
1.89 V
0V
0.51DV_DDR2
V
V
V
V
High-level input voltage, PCI
V_IH
High-level input voltage, I2C
0.5DV_DD33
0.7DV_DD33
High-level input voltage, non-DDR I/O, 1.8 V
0.65V_DDR2
Low-level input voltage, 3.3 V (except PCI-capable and I2C
pins)
V
V
V
0.8 V
Low-level input voltage, PCI
V_IL
Low-level input voltage, I2C
0.3DV_DD33
V
0
0.3DV_DD33
V
Low-level input voltage, non-DDR I/O, 1.8 V
0.35V_DDR2
V
T_c
Operating case temperature
Default
0
85 °C
F_SYSCLK1
DSP Operating Frequency (SYSCLK1)
20
594 MHz
(1) Future variants of TI SoC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance
options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,
1.1 V, 1.14 V, 1.2 V, 1.26 V with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin
configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI SoC
devices.
(2) Oscillator 1.8 V power supply (DEV_DV_DD18) can be connected to the same 1.8 V power supply as DV_DDR2.
(3) Oscillator ground (DEV_V_SS and AUX_V_SS) must be kept separate from other grounds and connected directly to the crystal load
capacitor ground.
(4) DDR_VREF is expected to equal 0.5DV_DDR2 of the transmitting device and to track variations in the DV_DDR2.
134 Device Operating Conditions
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