TMS320DM6467 Datasheet, PDF (248/334 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403 – DECEMBER 2007
6.17.4 HPI Electrical Data/Timing
www.ti.com
Table 6-72. Timing Requirements for Host-Port Interface Cycles⁽¹⁾⁽²⁾ (see Figure 6-50 through Figure 6-53)
NO.
1
t_{su(SELV-HSTBL)}
2
t_{h(HSTBL-SELV)}
3
t_w(HSTBL)
4
t_w(HSTBH)
11
t_{su(HDV-HSTBH)}
12
t_h(HSTBH-HDV)
13
t_{h(HRDYL-HSTBL)}
Setup time, select signals⁽³⁾ valid before HSTROBE low
Hold time, select signals⁽³⁾ valid after HSTROBE low
Pulse duration, HSTROBE active low
Pulse duration, HSTROBE inactive high between consecutive accesses
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
-594
MIN
5
2
15
2M
5
0
MAX
UNIT
ns
ns
ns
ns
ns
ns
0
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) M = SYSCLK3 period = (CPU clock frequency)/4 in ns. For example, when running parts at 594 MHz, use M = M = 1.68 ns.
(3) Select signals include: HCNTL[1:0], HR/W. For HPI16 mode only, select signals also includes HHWIL.
248 Peripheral Information and Electrical Specifications
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