BQ24262_15 Datasheet, PDF (5/56 Pages) Texas Instruments – bq2426x 3-A, 30-V, Host-Controlled Single-Input, Single-Cell Switched-Mode Li-Ion Battery Charger With Power-Path Management and USB-OTG Support

Not Recommended for New Designs : bq24260, bq24261
www.ti.com
bq24260, bq24261, bq24261M, bq24262
SLUSBU4D – DECEMBER 2013 – REVISED APRIL 2015
NAME
AGND
BAT
BGATE
BOOT
CD
D+
D–
DRV
IN
INT
PGND
PMID
PSEL
SCL
SDA
STAT
SW
SYS
TS
Thermal
Pad
PIN
bq24260
DSBGA VQFN
F1
12, 20
bq24261/1M/2
DSBGA VQFN
F1
12, 20
F3-F6 8, 9 F3-F6 8, 9
F2
11
F2
11
C6
2
C6
2
C5
4
C5
4
D4
14
–
–
D3
15
–
–
D6
3
D6
3
C1-C4 18, 19 C1-C4 18, 19
E2
10
E2
10
A1-A6
B1
21,22
1
A1-A6
B1
21,22
1
–
–
D4
14
D2
16
D2
16
D1
17
D1
17
E1
13
E1
13
B2-B6 23, 24 B2-B6 23, 24
E3-E6 6, 7 E3-E6 6, 7
D5
5
D5
5
–
–
–
–
Pin Functions
I/O
DESCRIPTION
Analog Ground. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.
I/O
Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at
least 1 μF of ceramic capacitance. See Application and Implementation for additional details.
External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET
O
to provide a very low resistance discharge path. Connect BGATE to the gate of the external
MOSFET. BGATE is low during high impedance mode or when no input is connected. If no
external FET is required, leave BGATE disconnected. Do not connect BGATE to GND.
I
High Side MOSFET Gate Driver Supply. Connect 0.033 µF of ceramic capacitance (voltage
rating > 10 V) from BOOT to SW to supply the gate drive for the high side MOSFET.
I
IC Hardware Disable Input. Drive CD high to place the bq24260/1/1M/2 in hi-z mode. Drive CD
low for normal operation. CD is pulled low internally with 100 kΩ.
I D+ and D– Connections for USB Input Adapter Detection. When a source is initially connected
to the input during DEFAULT mode, and a short is detected between D+ and D–, the input
I _{current limit is set to 1.5 A. If a short is not detected, the USB100 mode is selected.}
Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass
O
DRV to PGND with a 10-V or higher rated, +/-10%, X5R or better 2.2 µF ceramic capacitor. DRV
may be used to drive external loads up to 10mA. DRV is active whenever the input is connected
and V_IN > V_UVLO and V_IN > (V_BAT + V_SLP).
I
DC Input Power Supply. IN is connected to the external DC supply (AC adapter or USB port).
Bypass IN to PGND with at least a 4.7 μF of ceramic capacitance.
Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT
pulls low during charging. INT is high impedance when charging is complete, disabled or the
O charger is in high impedance mode. When a fault occurs, a 128-μs pulse is sent out as an
interrupt for the host. INT is enabled /disabled using the EN_STAT bit in the control register.
Connect INT to a logic rail through a 100-kΩ resistor to communicate with the host processor.
– Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.
I
High Side Bypass Connection. Connect at least 1 µF of ceramic capacitance from PMID to
PGND as close to the PMID and PGND terminals as possible.
Hardware Input Current Limit. In DEFAULT mode, PSEL selects the input current limit. Drive
I PSEL high to select USB100 (bq24261/1M) or USB500 (bq24262) mode, drive PSEL low to
select 1.5 A mode.
I I²C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor. Do not leave floating.
I/O I²C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.
Status Output. STAT is an open-drain output that signals charging status and fault interrupts.
STAT pulls low during charging. STAT is high impedance when charging is complete, disabled
O
or the charger is high impedance mode. When a fault occurs, a 128-μs pulse is sent out as an
interrupt for the host. STAT is enabled /disabled using the EN_STAT bit in the control register.
Connect STAT to a logic rail using an LED for visual indication or through a 100-kΩ resistor to
communicate with the host processor.
O
Inductor Connection. Connect to the switched side of the external inductor. The inductance must
be between 1.5 µH and 2.2 µH.
System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the
I
output bulk capacitors. Bypass SYS locally with at least 10 μF of ceramic capacitance. The SYS
rail must have at least 20 µF of total capacitance for stable operation. See Application and
Implementation for additional details.
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND.
The NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA
I compatibility. TS faults are reported by the I²C interface. Pull TS high to V_DRV to disable the TS
function if unused. See the NTC Monitor section for more details on operation and selecting the
resistor values.
There is an internal electrical connection between the exposed thermal pad and the PGND
–
terminal of the device. The thermal pad must be connected to the same potential as the PGND
terminal on the printed circuit board. Do not use the thermal pad as the primary ground input for
the device. PGND terminal must be connected to ground at all times.
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