BQ24262_15 Datasheet, PDF (43/56 Pages) Texas Instruments – bq2426x 3-A, 30-V, Host-Controlled Single-Input, Single-Cell Switched-Mode Li-Ion Battery Charger With Power-Path Management and USB-OTG Support

Not Recommended for New Designs : bq24260, bq24261
www.ti.com
11 Power Supply Recommendations
bq24260, bq24261, bq24261M, bq24262
SLUSBU4D – DECEMBER 2013 – REVISED APRIL 2015
11.1 Requirements for SYS Output
In order to provide an output voltage on SYS, the bq2426x requires either a power supply between 4.2 V and 6 V
input on all versions, 4.2 V and 6.5 V for IN input on bq24262, 4.2 V and 10.5 V on bq24260, and 4.2 and 14 V
on bq24261/M with at least 100 mA current rating connected to IN; or, a single-cell Li-Ion battery with voltage >
VBATUVLO connected to BAT. The source current rating must be at least 2.5 A for the buck converter of the
charger to provide maximum output power to SYS.
11.2 Requirements for Charging
In order for charging to occur the source voltage measured at the IN terminals of the IC, factoring in cable/trace
losses from the source, must be greater than the VINDPM threshold, but less than the maximum values shown
above. The current rating of the source must be higher than the buck converter needs to provide the load on
SYS. For charging at a desired charge current of I_CHRG, V_IN × I_IN × η > V_SYS × (_ISYS+ I_CHRG) where η is the
efficiency estimate from Figure 2 or Figure 3 and VSYS = VBAT when VBAT charges above VMINSYS. The
charger limits I_IN to the current limit setting of that input. With ISYS = 0 A, the charger consumes maximum
power at the end of CC mode, when the voltage at the BAT terminal is near VBATREG but ICHRG has not
started to taper off toward ITERM.
12 Layout
12.1 Layout Guidelines
The following provides some guidelines:
• Place 1-µF input capacitor as close to PMID terminal and PGND terminal as possible to make high-frequency
current loop area as small as possible.
• Connect the GND of the PMID and IN capacitors as close as possible.
• Place 4.7-µF input capacitor as close to IN terminal and PGND terminal as possible to make high-frequency
current loop area as small as possible.
• The local bypass capacitor from SYS to GND should be connected between the SYS terminal and PGND of
the IC. The intent is to minimize the current path loop area from the SW terminal through the LC filter and
back to the PGND terminal.
• Place all decoupling capacitors close to their respective IC terminal and as close as to PGND as possible. Do
not place components such that routing interrupts power stage currents. All small control signals should be
routed away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias.
Two vias per capacitor for power-stage capacitors and one via per capacitor for small-signal components. TI
also recommends putting vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-
coupling and ground-bounce issues. A single ground plane for this design gives good results.
• The high-current charge paths into IN, BAT, SYS and from the SW terminals must be sized appropriately for
the maximum charge current in order to avoid voltage drops in these traces. The PGND terminals should be
connected to the ground plane to return current through the internal low-side FET.
• For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance as the board pulls heat away from the IC.
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Product Folder Links: bq24260 bq24261 bq24261M bq24262