BQ24262_15 Datasheet, PDF (27/56 Pages) Texas Instruments – bq2426x 3-A, 30-V, Host-Controlled Single-Input, Single-Cell Switched-Mode Li-Ion Battery Charger With Power-Path Management and USB-OTG Support

Not Recommended for New Designs : bq24260, bq24261
www.ti.com
bq24260, bq24261, bq24261M, bq24262
SLUSBU4D – DECEMBER 2013 – REVISED APRIL 2015
9.4.19.4 Watchdog Timer in Boost Mode
During boost mode, the watchdog timer is active. The watchdog timer works the same as in charge mode. Write
a 1 to the TMR_RST reset bit in the control register. If the watchdog timer expires, the IC resets the EN_BOOST
bit to 0, signals the fault pulse on the STAT and INT terminals. The FAULT_x bits read "Low Supply Fault" as
this is a higher priority fault than the WD timer.
9.4.19.5 STAT/ INT During Boost Mode
During boost mode, the STAT and INT outputs are high impedance. Under fault conditions, a 128-µs pulse is
sent out to notify the host of the error condition.
9.4.19.6 Protection in Boost Mode
9.4.19.6.1 Output Overvoltage Protection
The bq24260/1/1M/2 contains integrated overvoltage protection on the IN terminal. During boost mode, if an
overvoltage condition is detected (V_IN > V_BOOSTOVP), after deglitch t_{DGL(BOOST_OVP)}, the IC turns off the PWM
converter, resets EN_BOOST bit to 0, sets fault status bits and sends out a fault pulse on STAT and INT. The
converter does not restart when VIN drops to the normal level until the EN_BOOST bit is reset to 1.
9.4.19.6.2 Output Overcurrent Protection
The bq24260/1/1M/2 contains overcurrent protection to prevent the device and battery damage when IN is
overloaded. When an overcurrent condition occurs, the cycle-by-cycle current limit limits the current from the
battery to the load. If the overload condition lasts for 8 ms, the overload fault is detected. When an overload
condition is detected, the bq24260/1/1M/2 turns off the PWM converter, resets EN_BOOST bit to 0, sets the fault
status bits and sends out the fault pulse on STAT and INT. The boost operation starts only after the fault is
cleared and the EN_BOOST bit is reset to 1 using the I²C.
9.4.19.6.3 Battery Voltage Protection
During boost mode, when the battery voltage is below the minimum battery voltage threshold, V_BATUVLO, the IC
turns off the PWM converter, resets EN_BOOST bit to 0, sets fault status bits and sends out a fault pulse on
STAT and INT. Once the battery voltage returns to the acceptable level, the boost starts only after the
EN_BOOST bit is set to 1. Proper operation below 3.3 V down to the V_BATUVLOis not specified.
9.5 Programming
9.5.1 Serial Interface Description
The bq24260 uses an I²C compatible interface to program charge parameters. I²C is a 2-wire serial interface
developed by NXP (formerly Philips Semiconductor, see I²C-Bus Specification, Version 5, October 2012). The
bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA
and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open-drain I/O
terminals, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the
bus. The master is responsible for generating the SCL signal and device addresses. The master also generates
specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits
data on the bus under control of the master device.
The bq24260/1/1M/2 device works as a slave and supports the following data transfer modes, as defined in the
I²C Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to
the battery charge solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. The I²C circuitry is powered from IN when a supply is connected. If the
IN supply is not connected, the I²C circuitry is powered from the battery through BAT. The battery voltage must
stay above V_BATUVLO with no input connected in order to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The bq24260/1/1M/2 device only supports 7-bit addressing. The device 7-bit address
is defined as ‘1101011’ (0x6Bh).
To avoid I²C hang-ups, a timer (t_I2CRESET) runs during I²C transactions. If the transaction takes longer than
t_I2CRESET, any additional commands are ignored and the I²C engine is reset. The timeout is reset with START and
repeated START conditions and stops when a valid STOP condition is sent.
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Product Folder Links: bq24260 bq24261 bq24261M bq24262