BQ24262_15 Datasheet, PDF (10/56 Pages) Texas Instruments – bq2426x 3-A, 30-V, Host-Controlled Single-Input, Single-Cell Switched-Mode Li-Ion Battery Charger With Power-Path Management and USB-OTG Support

Not Recommended for New Designs : bq24260, bq24261
bq24260, bq24261, bq24261M, bq24262
SLUSBU4D – DECEMBER 2013 – REVISED APRIL 2015
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Electrical Characteristics (continued)
Circuit of Figure 7, V_UVLO < V_IN < V_OVP AND V_IN > V_BAT+ V_SLP, T_J = –40°C to 125°C and T_J = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V_{BOVP_HYS}
t_DGL(BOVP)
I_CbCLIMIT
T_SHTDWN
V_BOVP hysteresis
BOVP Deglitch
Cycle-by-cycle current limit
Thermal trip
Thermal hysteresis
Lower limit for V_BAT falling from above V_BOVP
Battery entering/exiting BOVP
V_SYS shorted
1
% of
V_BATREG
8
ms
4.1
4.5
4.9
A
150
°C
10
°C
T_REG
Thermal regulation threshold Input current begins to cut off
Safety Timer Accuracy
–20%
125
°C
20%
PWM
R_{DSON_Q1}
Internal top MOSFET ON-
resistance
YFF Package: Measured from IN to SW
RGE Package: Measured from IN to SW
75
120 mΩ
80
135 mΩ
R_{DSON_Q2}
Internal bottom N-channel
MOSFET ON-resistance
YFF Package: Measured from SW to PGND
RGE Package: Measured from SW to PGND
75
115 mΩ
80
135 mΩ
f_OSC
Oscillator frequency
D_MAX
Maximum duty cycle
D_MIN
Minimum duty cycle
BATTERY-PACK NTC MONITOR (1)
1.35
1.5
1.65 MHz
95%
—
0%
V_HOT
V_WARM
V_COOL
V_COLD
TSOFF
High temperature threshold
Warm temperature threshold
Cool temperature threshold
Low temperature threshold
TS Disable threshold
t_DGL(TS)
Deglitch time on TS change
I²C-COMPATIBLE INTERFACE
V_TS falling, 2% V_DRV Hysteresis
V_TS falling, 2% V_DRV Hysteresis
V_TS rising, 2% V_DRV Hysteresis
V_TS rising, 2% V_DRV Hysteresis
V_TS rising, 4% V_DRV Hysteresis
Applies to V_HOT, V_WARM, V_COOL and V_COLD
27.3
36.0
54.7
58.2
80
30
38.3
56.4
60
50
32.6
41.2
58.1
61.8
85
%V_DRV
%V_DRV
%V_DRV
%V_DRV
%V_DRV
ms
V_IH
Input low threshold level
V_IL
Input low threshold level
V_OL
Output low threshold level
I_BIAS
High-Level leakage current
t_WATCHDOG
t_I2CRESET
OTG BOOST SUPPLY
V_PULL-UP=1.8 V, SDA and SCL
V_PULL-UP=1.8 V, SDA and SCL
IL=5 mA, sink current
V_PULL-UP=1.8 V, SDA and SCL
1.3
V
0.4
V
0.4
V
1 μA
30
50
s
700
ms
I_{QBAT_ BOOST}
Quiescent current during
boost mode (BAT pin)
3.3 V < V_BAT < 4.5 V, no switching
100 µA
Battery voltage range for
specified boost operation
VBAT falling
3.3
4.5
V
V_{IN_BOOST}
Boost output voltage (to pin
VBUS)
3.3 V < V_BAT < 4.5 V over line and load
4.95
5.05
5.2
V
I_BO
Maximum output current for
boost
3.3 V < V_BAT < 4.5 V
BOOST_ILIM = 1
BOOST_ILIM = 0
1000
500
mA
I_BLIMIT
Cycle by cycle current limit for
boost (measured at low-side 3.3 V < V_BAT < 4.5 V
FET)
BOOST_ILIM = 1
BOOST_ILIM = 0
4
A
2
V_BOOSTOVP
Overvoltage protection
threshold for boost (IN pin)
Signals fault and exits boost mode
5.8
6
6.2
V
t_{DGL(BOOST_OVP)}
Deglitch Time, VIN OVP in
Boost Mode
170
µs
V_BURST(ENT)
Upper V_IN voltage threshold to
enter burst mode (stop
switching)
5.1
5.2
5.3
V
V_BURST(EXIT)
Lower V_BUS voltage threshold
to exit burst mode (start
switching)
4.9
5
5.1
V
10
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