TMS320C6455_15 Datasheet, PDF (4/257 Pages) Texas Instruments – TMS320C6455 Fixed-Point Digital Signal Processor

TMS320C6455
SPRS276M – MAY 2005 – REVISED MARCH 2012
1.3 Functional Block Diagram
Figure 1-2 shows the functional block diagram of the C6455 device.
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32
DDR2 SDRAM
SBSRAM
ZBT SRAM
64
SRAM
ROM/FLASH
I/O Devices
DDR2
Mem Ctlr
PLL2 and
PLL2
Controller^(D)
EMIFA
TCP2
VCP2
McBSP0^(A)
McBSP1^(A)
Serial
RapidIO
HPI (32/16)^(B)
PCI66^(B)
UTOPIA^(B)
EMAC
10/100/1000
MII
RMII
GMII
RMGII^(D)
MDIO
16
GPIO16^(B)
I2C
Timer1^(C)
HI
LO
Timer1^(C)
HI
LO
Primary
Switched
Central
Resource
C6455
L1P SRAM/Cache Direct-Mapped
32K Bytes
L2 ROM
32K
Bytes^(E)
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
C64x+ DSP Core
Instruction Fetch
Control Registers
16-/32-bit
Instruction Dispatch
SPLOOP Buffer
L2Cache
Memory ^M
Instruction
Decode
In-Circuit Emulation
2048K
e
Bytes
g
a
m
o
Data Path A
A Register File
A31−A16
Data Path B
B Register File
B31−B16
d
A15−A0
B15−B0
u
l
e
.M1
.M2
.L1 .S1 xx .D1 .D2 xx .S2 .L2
xx
xx
L1D Memory Controller (Memory Protect/Bandwidth Mgmt)
L1D SRAM/Cache
2-Way Set-Associative
32K Bytes Total
EDMA 3.0
Secondary
Switched Central
Resource
PLL1 and
PLL1
Controller
Device
Configuration
Logic
Boot Configuration
A. McBSPs: Framing Chips - H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs.
B. The PCI peripheral pins are muxed with some of the HPI peripheral pins and the UTOPIA address pins.
For more detailed information, see the Device Configuration section.
C. Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as a 64-bit general-purpose timer, dual 32-bit general-purpose timers,
or a watchdog timer.
D. The PLL2 controller also generates clocks for the EMAC.
E. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
Figure 1-2. Functional Block Diagram
4
Features
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