TMS320C6455_15 Datasheet, PDF (151/257 Pages) Texas Instruments – TMS320C6455 Fixed-Point Digital Signal Processor

TMS320C6455
www.ti.com
SPRS276M – MAY 2005 – REVISED MARCH 2012
7.8.3.2 PLL Controller Command Register
The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is
shown in Figure 7-25 and described in Table 7-34.
31
16
Reserved
R-0
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
1
0
Rsvd GOSET
R/W-0 R/W-0
Figure 7-25. PLL Controller Command Register (PLLCMD) [Hex Address: 029C 0138]
Table 7-34. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit Field
31:2 Reserved
1 Reserved
0 GOSET
Value
0
0
1
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1
to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous
GO operations have completed.
No effect. Write of 0 clears bit to 0.
Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further
writes of 1 can initiate the GO operation.
Copyright © 2005–2012, Texas Instruments Incorporated
C64x+ Peripheral Information and Electrical Specifications 151
Submit Documentation Feedback
Product Folder Link(s): TMS320C6455