TMS320C6455_15 Datasheet, PDF (25/257 Pages) Texas Instruments – TMS320C6455 Fixed-Point Digital Signal Processor

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URDATA7/MRXD7
URDATA6/MRXD6
URDATA5/MRXD5
URDATA4/MRXD4
URDATA3/MRXD3
URDATA2/MRXD2
URDATA1/MRXD1/RMRXD1
URDATA0/MRXD0/RMRXD0
URENB/MRXDV
URADDR4/PCLK/GP[2]
URADDR3/PREQ/GP[15]
URADDR2/PINTA/GP[14]
URADDR1/PRST/GP[13]
URADDR0/PGNT/GP[12]
URCLAV/MCRS/RMCRSDV
URSOC/MRXER/RMRXER
URCLK/MRCLK
UTOPIA (SLAVE)^(A)
TMS320C6455
SPRS276M – MAY 2005 – REVISED MARCH 2012
Receive
Transmit
UXDATA7/MTXD7
UXDATA6/MTXD6
UXDATA5/MTXD5
UXDATA4/MTXD4
UXDATA3/MTXD3
UXDATA2/MTXD2
UXDATA1/MTXD1/RMTXD1
UXDATA0/MTXD0/RMTXD0
Control/Status
Control/Status
Clock
Clock
UXENB/MTXEN/RMTXEN
UXADDR4/MDCLK
UXADDR3/MDIO
UXADDR2/PCBE3
UXADDR1/PIDSEL
UXADDR0/PTRDY
UXCLAV/GMTCLK
UXSOC/MCOL/TCLKRISE
UXCLK/MTCLK/
RMREFCLK
A. These UTOPIA pins are muxed with the PCI or EMAC or GPIO peripherals. By default, these signals function as GPIO or EMAC peripheral
pins or have no function. For more details on these muxed pins, see the Device Configuration section of this document.
Figure 2-11. UTOPIA Peripheral Signals
32
HD[15:0]/AD[15:0]
HD[31:16]/AD[31:16]
UXADDR2/PCBE3
HR/W/PCBE2
HDS2/PCBE1
UXADDR4/PCBE0/GP[2]
Data/Address
Command
Byte Enable
Clock
Control
URADDR0/PGNT/GP[12]
URADDR3/PREQ/GP[15]
Arbitration
Error
HHWIL/PCLK
UXADDR1/PIDSEL
HCNTL1/PDEVSEL
HINT/PFRAME
URADDR2/PINTA/GP[14]
HAS/PPAR
URADDR1/PRST/GP[13]
HRDY/PIRDY
HCNTL0/PSTOP
UXADDR0/PTRDY
HDS1/PSERR
HCS/PPERR
PCI Interface^(A)
A. These PCI pins are muxed with the HPI or UTOPIA or GPIO peripherals. By default, these signals function as GPIO or EMAC. For more details
on these muxed pins, see the Device Configuration section of this document.
Figure 2-12. PCI Peripheral Signals
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