TMS320C6455_15 Datasheet, PDF (13/257 Pages) Texas Instruments – TMS320C6455 Fixed-Point Digital Signal Processor

TMS320C6455
www.ti.com
SPRS276M – MAY 2005 – REVISED MARCH 2012
2.4 Boot Sequence
The boot sequence is a process by which the DSP's internal memory is loaded with program and data
sections and the DSP's internal registers are programmed with predetermined values. The boot sequence
is started automatically after each power-on reset, warm reset, max reset, and system reset. For more
details on the initiators of these resets, see Section 7.6, Reset Controller.
There are several methods by which the memory and register initialization can take place. Each of these
methods is referred to as a boot mode. The boot mode to be used is selected at reset through the
BOOTMODE[3:0] pins.
Each boot mode can be classified as a hardware boot mode or as a software boot mode. Software boot
modes require the use of the on-chip bootloader. The bootloader is DSP code that transfers application
code from an external source into internal or external program memory after the DSP is taken out of reset.
The bootloader is permanently stored in the internal ROM of the DSP starting at byte address 0010
0000h. Hardware boot modes are carried out by the boot configuration logic. The boot configuration logic
is actual hardware that does not require the execution of DSP code. Section 2.4.1, Boot Modes
Supported, describes each boot mode in more detail.
When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
Therefore, when using a software boot mode, care must be taken such that the CPU frequency does not
exceed 750 MHz at any point during the boot sequence. After the boot sequence has completed, the CPU
frequency can be programmed to the frequency required by the application.
2.4.1 Boot Modes Supported
The C6455 device has six boot modes:
• No boot (BOOTMODE[3:0] = 0000b)
With no boot, the CPU executes directly from the internal L2 SRAM located at address 0x80 0000.
Note: device operations is undefined if invalid code is located at address 0x80 0000. This boot mode is
a hardware boot mode.
• Host boot (BOOTMODE[3:0] = 0001b and BOOTMODE[3:0] = 0111b)
If host boot is selected, after reset, the CPU is internally "stalled" while the remainder of the device is
released. During this period, an external host can initialize the CPU's memory space as necessary
through Host Port Interface (HPI) or the Peripheral Component Interconnect (PCI) interface. Internal
configuration registers, such as those that control the EMIF can also be initialized by the host with two
exceptions: Device State Control registers (Section 3.4), PLL1 and PLL2 Controller registers
(Section 7.7 and Section 7.8) cannot be accessed through any host interface, including HPI and PCI.
Once the host is finished with all necessary initialization, it must generate a DSP interrupt (DSPINT) to
complete the boot process. This transition causes boot configuration logic to bring the CPU out of the
"stalled" state. The CPU then begins execution from the internal L2 SRAM located at 0x80 0000. Note
that the DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This event
must be cleared by software before triggering transfers on DMA channel 0.
All memory, with the exceptions previously described, may be written to and read by the host. This
allows for the host to verify what it sends to the DSP if required. After the CPU is out of the "stalled"
state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
As previously mentioned, for the C6455 device, the Host Port Interface (HPI) and the Peripheral
Component Interconnect (PCI) interface can be used for host boot. To use the HPI for host boot, the
PCI_EN pin (Y29) must be low [default] (enabling the HPI peripheral) and BOOTMODE[3:0] must be
set to 0001b at device reset. Conversely, to use the PCI interface for host boot, the PCI_EN pin (Y29)
must be high (enabling the PCI peripheral) and BOOTMODE[3:0] must be set to 0111b at device reset.
For the HPI host boot, the DSP interrupt can be generated through the use of the DSPINT bit in the
HPI Control (HPIC) register.
For the HPI host boot, the CPU is actually held in reset until a DSP interrupt is generated by the host.
The DSP interrupt can be generated through the use of the DSPINT bit in the HPI Control (HPIC)
register. Since the CPU is held in reset during HPI host boot, it will not respond to emulation software
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