TMS320C6455_15 Datasheet, PDF (1/257 Pages) Texas Instruments – TMS320C6455 Fixed-Point Digital Signal Processor

TMS320C6455
www.ti.com
SPRS276M – MAY 2005 – REVISED MARCH 2012
TMS320C6455 Fixed-Point Digital Signal Processor
Check for Samples: TMS320C6455
1 Features
12
• High-Performance Fixed-Point DSP (C6455)
– 1.25-, 2.5-, 3.125-Gbps Link Rates
– 1.39-, 1.17-, 1-, 0.83-ns Instruction Cycle
Time
– Message Passing, DirectIO Support, Error
Mgmt Extensions, Congestion Control
– 720-MHz, 850-MHz, 1-GHz, 1.2-GHz Clock
– IEEE 1149.6 Compliant I/Os
Rate
• DDR2 Memory Controller
– Eight 32-Bit Instructions/Cycle
– Interfaces to DDR2-533 SDRAM
– 9600 MIPS/MMACS (16-Bits)
– 32-Bit/16-Bit, 533-MHz (data rate) Bus
– Commercial Temperature [0°C to 90°C]
– 512M-Byte Total Addressable External
– Extended Temperature [-40°C to 105°C]
Memory Space
• TMS320C64x+™ DSP Core
• EDMA3 Controller (64 Independent Channels)
– Dedicated SPLOOP Instruction
• 32-/16-Bit Host-Port Interface (HPI)
– Compact Instructions (16-Bit)
– Instruction Set Enhancements
– Exception Handling
• TMS320C64x+ Megamodule L1/L2 Memory
Architecture:
– 256K-Bit (32K-Byte) L1P Program Cache
[Direct Mapped]
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Local Bus Specification (v2.3)
• One Inter-Integrated Circuit (I²C) Bus
• Two McBSPs
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
– 256K-Bit (32K-Byte) L1D Data Cache
[2-Way Set-Associative]
– Supports Multiple Media Independent
Interfaces (MII, GMII, RMII, and RGMII)
– 16M-Bit (2048K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
– 8 Independent Transmit (TX) and
8 Independent Receive (RX) Channels
– 256K-Bit (32K-Byte) L2 ROM
– Time Stamp Counter
• Enhanced Viterbi Decoder Coprocessor (VCP2)
– Supports Over 694 7.95-Kbps AMR
– Programmable Code Parameters
• Enhanced Turbo Decoder Coprocessor (TCP2)
– Supports up to Eight 2-Mbps 3GPP
(6 Iterations)
– Programmable Turbo Code and Decoding
Parameters
• Endianess: Little Endian, Big Endian
• 64-Bit External Memory Interface (EMIFA)
– Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EEPROM) and
Synchronous Memories (SBSRAM, ZBT
• Two 64-Bit General-Purpose Timers,
Configurable as Four 32-Bit Timers
• UTOPIA
– UTOPIA Level 2 Slave ATM Controller
– 8-Bit Transmit and Receive Operations up to
50 MHz per Direction
– User-Defined Cell Format up to 64 Bytes
• 16 General-Purpose I/O (GPIO) Pins
• System PLL and PLL Controller
• Secondary PLL and PLL Controller, Dedicated
to EMAC and DDR2 Memory Controller
• Advanced Event Triggering (AET) Compatible
• Trace-Enabled Device
• IEEE-1149.1 (JTAG™) Boundary-Scan-
Compatible
SRAM)
• 697-Pin Ball Grid Array (BGA) Package
– Supports Interface to Standard Sync Devices
(CTZ, GTZ, or ZTZ Suffix), 0.8-mm Ball Pitch
and Custom Logic
• 0.09-μm/7-Level Cu Metal Process (CMOS)
(FPGA, CPLD, ASICs, etc.)
• 3.3-/1.8-/1.5-/1.25-/1.2-V I/Os,
– 32M-Byte Total Addressable External
1.25-/1.2-V Internal
Memory Space
• Four 1x Serial RapidIO® Links (or One 4x),
v1.2 Compliant
1
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2
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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