TLC320AD75C Datasheet, PDF (23/43 Pages) Texas Instruments – 20-Bit Sigma-Delta Stereo ADA Circuit

Table 2–4. System Mode Register^†
D16 D15 D14 D13 D12–D5 D4 D3 D2 D1
DESCRIPTION
0
-
-
-
-
- - - - Reserved
-
0
-
-
-
----
Off
Resynchronize
-
1
-
-
-
----
On
-
- 00
-
----
44.1 kHz
-
- 01
-
- - - - ^{Sample rate/}
de-emphasis
-
- 10
-
-
-
-
- _selection
-
- 11
-
----
Reserved
48 kHz
32 kHz
-
-
-
-
0
- - - - Reserved
-
-
-
-
-
0- - -
20 bits audio data
Input-data word width
-
-
-
-
-
1- - -
16 bits audio data
-
-
-
-
-
-0- -
MSB first
Input D-data protocol
-
-
-
-
-
-1- -
LSB first
-
-
-
-
-
- -0-
DAC register select
Attenuator-mode
register
-
-
-
-
-
-
1-
System-mode register
-
-
-
-
-
-
-
-
-
-
† _{The initialization value is 0000h.}
- - -0
DAC mode
- - -1
Normal
Factory test only
2.19 Auto-Resynchronization Functionality
The TLC320AD75C has an auto-resynchronization function to keep the entire coversion cycle for the ADC
" ^{portion and DAC portion respectively checking the LRCK cycle of the fs rate. When the ADC is in slave mode,}
the ADC portion has a window of 4 clocks of the internal 64 f_s clock to check the LRCK cycle with the f_s
rate detecting the rising edge of LRCK within this window. When an error is detected on the LRCK cycle,
the ADC conversion cycle is resynchronized with an external LRCK cycle at the next rising edge of LRCK.
This resynchronization occurrs automatically and the ADC portion continues processing based on the new
conversion cycle timing.
" The DAC portion has a window of 2 clocks of the internal 128 f_s clock to check the LRCK cycle detecting
the rising edge of the LRCK clock. When an error is detected, the conversion cycle of the DAC is
resynchronized with an external LRCK cycle automatically and the DAC portion continues processing based
on the new conversion cycle timing. (The external LRCK rate should be the same as the fs rate. This
functionality is to ensure the TLC320AD75C conversion operation even if LRCK has a timing problem due
to noise injection for example.)
2–11