TLC320AD75C Datasheet, PDF (14/43 Pages) Texas Instruments – 20-Bit Sigma-Delta Stereo ADA Circuit

During general operation of the ADC, APD is recommended to be pulled high (APD is not needed for a reset).
When using the analog power-down mode (APD low), the following timing procedure is required to start all
of the ADC since the analog modulator portion which includes the external portion needs to be settled after
APD is high.
APD
DPD
> 100 msec
LRCKA
ADOUT
> 26 fs
Figure 2–1. ADC Start-Up Timing
2.1.3 Reset/ Initialization for DAC
When INIT is brought low, an internal reset signal becomes active approximately 120 cycles of the sampling
frequency (f_s) after the falling edge of INIT. Under this condition, all internal circuits are initialized and the
PWM output is held at zero data (50% duty cycle). When INIT is brought high, the internal reset signal goes
inactive for a maximum of five LRCKD periods after the rising edge of INIT. At this point, internal clocks are
synchronous with LRCKD and the PWM output is valid (see Figure 2–2). LRCKD must be applied for proper
initialization.
120 Cycles of fs
INIT
5 periods max
Internal
Reset
LRCKD
Figure 2–2. DAC-Reset Timing Relationships
2–2