TLC320AD75C Datasheet, PDF (17/43 Pages) Texas Instruments – 20-Bit Sigma-Delta Stereo ADA Circuit

2.7 Test
TEST1 and TEST2 are reserved for factory test and are tied to digital ground (V_SS1).
2.8 Master Mode for ADC
Configured as the master device (M_S is connected to V_DD1), the TLC320AD75C generates LRCKA and
SCLKA from MCLKI. These signals are provided for synchronizing the serial port of a digital signal processor
(DSP) or other control devices.
LRCKA is generated internally from MCLKI. The frequency of LRCKA is fixed at the sampling frequency,
f_s (MCLKI/256). During the high period of LRCKA, the left channel data is serially shifted to the output; during
the low period, the right channel data is shifted to the output (ADOUT). The conversion cycle is synchronized
with the rising edge of LRCKA.
Figure 2–4 (master mode) shows 20-bit data, MSB first, ADOUT data shifted out of the TLC320AD75 during
the first 20 SCLKA periods of the 32 SCLKA periods for both left and right channel data.
Output
SCLKA
ADOUT ^Output
MSB
19 18
20-BIT MASTER MODE
LSB
... 1 0
MSB
19 18 . . .
LSB
10
MSB
19 18
LRCKA _Output
Left
64 SCLKs
Right
Figure 2–4. ADC Audio-Data Serial Timing – Master Mode
2.9 Slave Mode for ADC
Configured as a slave device (M_S is connected to V_SS1), the TLC320AD75C receives LRCKA and SCLKA
as inputs. The conversion cycle is synchronized to the rising edge of LRCKA, and the data is synchronized
to the falling edge of SCLKA. SCLKA must meet the setup requirements specified in the recommended
operating conditions section. Synchronization of the slave mode is accomplished with the rising edge of
DPD.
The slave mode is shown in Figure 2–5. SCLKA and LRCKA are externally generated and sourced. The
first rising edges of SCLKA and LRCKA after the rising edge of DPD initiate the conversion cycle (see
Section 2.8, Master Mode for ADC for signal functions).
Figure 2–5 (slave mode) shows 20-bit data, MSB first, and ADOUT data shifted out of the TLC320AD75
during the first 20 SCLKA periods of the 32 SCLKA periods for both left and right channel data.
input
SCLKA
ADOUT ^output
LRCKA input
20-BIT SLAVE MODE
MSB
LSB
19 18 . . . 1 0
Left
MSB
LSB
19 18 . . . 1 0
64 SCLKs
Right
Figure 2–5. ADC Audio-Data Serial Timing – Slave Mode
2.10 Digital-Audio Data Interface for DAC
The conversion cycle is synchronized to the rising edge of LRCKD, and the data must meet the setup
requirements specified in the timing requirements table. The input data is 16 or 20 bits with the MSB or LSB
first as selected in the system register. The recommended SCLKD frequency is 64 × f_s. Figure 2–6
illustrates the input timing.
2–5