TLC320AD75C Datasheet, PDF (16/43 Pages) Texas Instruments – 20-Bit Sigma-Delta Stereo ADA Circuit

2.6 Master Clock
2.6.1 Master-Clock Circuit for ADC
The master-clock circuit generates and distributes necessary clocks throughout the device. MCLKI is the
external master-clock input. The sample rate of the data paths is set as LRCKA = MCLKI/256. With a fixed
oversampling ratio of 64 × f_s, the effect of changing MCLKI is shown in Table 2–1.
Table 2–1. ADC Master Clock to Sample-Rate Comparison
MCLKI SCLKA LRCKA
(MHz)
(MHz)
(kHz)
12.2880 3.0720
48
11.2896 2.8224
44.1
8.1920 2.0480
32
When the TLC320AD75C is in master mode (M_S is pulled high) SCLKA is derived from MCLKI in order
to provide clocking of the serial communications between the sigma-delta audio ADC and a digital signal
processor (DSP) or control logic. This is equivalent to a clock running at 64 × LRCKA.
When the TLC320AD75C is in slave mode (M_S is connected to V_SS1), SCLKA is externally derived. For
SCLKA use of a clock running at 64 times LRCKA is recommended.
2.6.2 Master-Clock Circuit for DAC
The timing and control circuit generates and distributes necessary clocks throughout the TLC320AD75C.
XIN is the oscillator input terminal or can receive an external master-clock input. The sample rate of the data
paths is set as LRCKD = XIN/512. With a fixed oversampling ratio of 32× and each PWM output value
requiring 16 XIN cycles, the effect of changing XIN is shown in Table 2–2.
Table 2–2. DAC Master Clock to Sample-Rate Comparison
XIN
(MHz)
256CK
(MHz)
LRCKD
(kHz)
24.5760
12.2880
48.0
22.5792
11.2896
44.1
16.3840
8.1920
32.0
The DAC can be operated at any conversion rate between 48 kHz and 32 kHz by choosing the appropriate
master-clock frequency. Some of the functions of the converter, such as the deemphasis filter, operate only
at the frequencies shown in Table 2–2.
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