TLC320AD75C Datasheet, PDF (12/43 Pages) Texas Instruments – 20-Bit Sigma-Delta Stereo ADA Circuit

Terminal Functions (Continued)
TERMINAL
I/O
NAME
NO.
DESCRIPTION
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{M_S}
47
I
Master/slave selection. The ADC serial port is configured as master mode when M_S
is pulled high. M_S is connected to VSS1 for slave mode.
NU
7, 8,
49, 50
– Not used
PVDDL
40
PWM power supply for left channel DAC
PVDDR
31
PWM power supply for right channel DAC
PVSSL
38
PWM ground for left channel DAC
PVSSR
33
PWM ground for right channel DAC
REFI
Input reference voltage. REFI provides reference voltage for the ADC modulator
3
I
(normally connected to REFO).
REFO
54
O Internal ADC reference voltage (normally connected to REFI).
R1
30
O Right channel DAC PWM output 1
R2
32
O Right channel DAC PWM output 2
SCLKA
Shift clock for the ADC. The shift clock clocks serial data out of the ADC, and operates
11
I/O at 64 times the sample rate (i.e. 64 times LRCKA). SCLKA is normally connected to
SCLKD. SCLKA is output when configured in master mode.
Shift clock for the DAC. The shift clock clocks serial audio data into the DAC, and
SCLKD
26
I
operates at 64 times the sample rate (i.e. 64 times LRCKD). SCLKD is normally
connected to SCLKA.
SHIFT
20
I
Shift data. SHIFT clocks the control data (CDIN) into the internal control registers for
the DAC.
TEST1
TEST2
XIN
9
I
Factory test terminal1. TEST1 should be connected to VSS1 for normal operation.
46
I
Factory test terminal2. TEST2 should be connected to VSS1 for normal operation.
36
I
Oscillator input terminal for 512 times the DAC sample rate. XIN derives all of the key
logic signals of the DAC device. (XIN can also be driven by an external oscillator.)
XOUT
35
O Oscillator output terminal for 512 times the DAC sample rate
VDD1
VDD2
VSS1
VSS1B
VSS2
VSS2B
V35A
V35D
XVDD
XVSS
256CK
43, 44
29, 42
45
14, 48
24
17
13
23
34
37
22
Digital power supply for ADC
Digital power supply voltage for DAC
Digital ground for ADC digital flters
Digital substrate ground for ADC
Digital ground for the DAC
Digital sustrate ground for DAC
Digital power supply for ADC interface logic. V35A is connected to 3 V or 5 V.
Digital power supply for DAC interface logic. V35D is connected to 3 V or 5 V.
Oscillator power-supply voltage for DAC
Oscillator circuit ground for DAC
O
256 times sample rate clock output. 256CK is normally connected to MCLKI through
a 50-Ω resistor. 256CK is the XIN frequency divided by two.
512CK
25
O
512 times sample rate clock output (output level is 3.3 V for V35D = 3.3 V). 512CK is
a buffered version of XIN (master clock input).
1–6