TLC320AD75C Datasheet, PDF (13/43 Pages) Texas Instruments – 20-Bit Sigma-Delta Stereo ADA Circuit

2 Detailed Description
The sigma-delta ADC converter consists of an oversampling analog modulator and digital decimation filter.
The sigma-delta DAC incorporates an interpolation finite impulse-response (FIR) filter and oversampled
modulator. The pulse-width-modulation (PWM) digital output feeds an external low-pass filter to recover the
analog audio signal.
Two control registers configure the DAC. The attenuation register controls the attenuation range,
de-emphasis enable, and mute selection. The system register controls the data format and de-emphasis
filter-sample rate.
2.1 Power-Down and Reset Functions
2.1.1 ADC Power Down
The power-down state is comprised of a separate digital and analog power down for the ADC. The power
consumption of each is detailed in the electrical characteristics section.
The digital power-down mode shuts down the digital filters and clock generators. When the digital
power-down terminal is pulled high, normal operation of the device is initiated. In slave mode, the conversion
process must synchronize to an input on LRCKA as well as SCLKA. Therefore, the conversion process is
not initiated until the first rising edges of both SCLKA and LRCKA are detected after DPD is pulled high. This
synchronizes the conversion cycle; all conversions are performed at a fixed LRCKA rate after the initial
synchronization. After DPD is brought high, the output of the digital filters remains invalid for 26 LRCKA
cycles which consists of group delays of the decimation and high-pass filter.
The analog power-down mode disables the analog modulators. The single-bit modulator outputs become
invalid, which renders the outputs of the digital filters invalid. When the APD terminal is brought high, the
modulators are brought back online; however, the settling time of the modulator stage is normally 100 ms.
2.1.2 Reset Function for ADC
The conversion process is not initiated until the first rising edges of both SCLKA and LRCKA are detected
after DPD is pulled high. This synchronizes the conversion cycle; all conversions are performed at a fixed
LRCKA rate after the initial synchronization.
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