TL16C552A Datasheet, PDF (20/39 Pages) Texas Instruments – DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
FIFO control register (FCR)
This write-only register is at the same location as the interrupt identification register. It enables and clears the
FIFOs, sets the trigger level of the receiver FIFO, and selects the type of DMA signaling.
D Bit 0: FCR0 enables both the transmitter and receiver FIFOs. All bytes in both FIFOs can be cleared by
clearing FCR0. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the
TL16C450 mode and vice versa. Programming of other FCR bits is enabled by setting FCR0.
D Bit 1: When set, FCR1 clears all bytes in the receiver FIFO and resets the counter. This does not clear the
shift register.
D Bit 2: When set, FCR2 clears all bytes in the transmitter FIFO and resets the counter. This does not clear
the shift register.
D Bit 3: When set, FCR3 changes the RXRDY and TXRDY terminals from mode 0 to mode 1 when FCR0
is set.
D Bits 4 and 5: FCR4 and FCR5 are reserved for future use.
D Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 4).
Table 4. Receiver FIFO Trigger Level
BIT
7
6
0
0
0
1
1
0
1
1
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
01
04
08
14
FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled:
1. LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is reset.
2. IIR = 06 receiver line status interrupt has higher priority than the received data available interrupt
IIR = 04.
3. Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by
the FIFO. When the FIFO drops below its programmed trigger level, it is cleared.
4. IIR = 04 (receive data available indicator) also occurs when the FIFO reaches its trigger level. It is
cleared when the FIFO drops below the programmed trigger level.
The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are
enabled.
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