TL16C552A Datasheet, PDF (13/39 Pages) Texas Instruments – DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

IOW
(WR THR)
SOUT
TXRDY
RCLK
CLK
TL16C450 Mode
SIN
(receiver input
data)
Sample
CLK
Interrupt
(data ready or
RCVR ERR)
IOR
TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
Byte #16
50%
Data
Parity
Stop
Start
Start of
Byte #16
tpd5
50%
FIFO Full
td8
50%
Figure 8. Transmitter Ready Mode 1 Timing Waveforms
8 CLK Cycles
tpd6
Start
Data Bits 5 – 8
Parity
Stop
td9
50%
tpd7
50%
Active
50%
Figure 9. Receiver Timing Waveforms
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