TL16C552A Datasheet, PDF (14/39 Pages) Texas Instruments – DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
SIN
Sample
CLK
Trigger
Interrupt
(FCR6, 7 = 0, 0)
IOR
(RD RBR)
LSI
Interrupt
IOR
(RD LSR)
SIN
Start _{Data Bits 5 – 8}
Parity Stop
50%
td9
50%
tpd7
Active
50%
50%
50%
50%
tpd7
Active
Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms
(FIFO at or above
trigger level)
(FIFO below
trigger level)
Stop
Sample
CLK
Time Out or
Trigger Level
Interrupt
LSI
Interrupt
IOR
(RD LSR)
td9
(see Note A)
50%
50%
td9
Top Byte of FIFO
tpd7
Active
50%
50%
50%
tpd7
(FIFO at or above
trigger level)
(FIFO below
trigger level)
IOR
(RD RBR)
Active
50%
Previous Byte
Read From FIFO
NOTE A: This is the reading of the last byte in the FIFO.
50%
Active
Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
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