TL16C552A Datasheet, PDF (15/39 Pages) Texas Instruments – DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
IOR
(RD RBR)
SIN
(first byte)
Stop
Sample
CLK
RXRDY
td9
(see Note B )
50%
50%
Active
(see Note A)
tpd8
50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, td9 = 3 RCLK cycles. For a time-out interrupt, td9 = 8 RCLK cycles.
Figure 12. Receiver Ready Mode 0 Waveforms
IOR
(RD RBR)
SIN
(first byte that reaches
the trigger level)
Stop
50%
Active
(see Note A)
Sample
CLK
td9
(see Note B)
RXRDY
50%
50%
tpd8
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 –1, td9 = 3 RCLK cycles. For a trigger change level interrupt, td9 = 8 RCLK.
Figure 13. Receiver Ready Mode 1 Waveforms
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
15