TL16C552A Datasheet, PDF (18/39 Pages) Texas Instruments – DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic
abbreviations for the internal registers are shown in Table 1.
Table 1. Internal Register Mnemonic Abbreviations
CONTROL
Line control register
FIFO control register
Modem control register
Divisor latch LSB
Divisor latch MSB
Interrupt enable register
MNEMONIC
STATUS
LCR
Line status register
FCR
Modem status register
MCR
DLL
DLM
IER
MNEMONIC
DATA
LSR
Receiver buffer register
MSR
Transmitter holding register
MNEMONIC
RBR
THR
The address, read, and write inputs are used with the divisor latch access bit (DLAB) in the line control register (bit 7)
to select the register to be written to or read from (see Table 2). Individual bits within the registers are referred to by
the register mnemonic and the bit number in parenthesis. As an example, LCR7 refers to line control register bit 7.
The transmitter holding register and receiver buffer register are data registers that hold from five to eight bits of data.
If fewer than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word is always the first
serial data bit received and transmitted. The ACE data registers are double buffered (TL16C450 mode) or FIFO
buffered (FIFO mode) so that read and write operations can be performed when the ACE is performing the
parallel-to-serial or serial-to-parallel conversion.
Table 2. Register Selection^†
DLAB A2
A1
A0 MNEMONIC
REGISTER
L
L
L
L
RBR
Receiver buffer register (read only)
L
L
L
L
THR
Transmitter holding register (write only)
L
L
L
H
IER
Interrupt enable register
X
L
H
L
IIR
Interrupt identification register (read only)
X
L
H
L
FCR
FIFO control register (write only)
X
L
H
H
LCR
Line control register
X
H
L
L
MCR
Modem control register
X
H
L
H
LSR
Line status register
X
H
H
L
MSR
Modem status register
X
H
H
H
SCR
Scratch pad register
H
L
L
L
DLL
LSB divisor latch
H
L
L
H
DLM
MSB divisor latch
† _{The serial channel is accessed when either CS0 or CS1 is low.}
X = irrelevant, L = low level, H = high level
18
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265