MSP430F551X_1 Datasheet, PDF (2/115 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F551x
MSP430F552x
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
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DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with extensive
low-power modes, is optimized to achieve extended battery life in portable measurement applications. The
device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to
active mode in less than 5 µs.
The MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 are microcontroller configurations with
integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 12-bit analog-to-digital
converter (ADC), two universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock
module with alarm capabilities, and 63 I/O pins. The MSP430F5528, MSP430F5526, MSP430F5524, and
MSP430F5522 include all of these peripherals but have 47 I/O pins.
The MSP430F5519, MSP430F5517, and MSP430F5515 are microcontroller configurations with integrated USB
and PHY supporting USB 2.0, four 16-bit timers, two universal serial communication interfaces (USCI), hardware
multiplier, DMA, real time clock module with alarm capabilities, and 63 I/O pins. The MSP430F5514 and
MSP430FF5513 include all of these peripherals but have 47 I/O pins.
Typical applications include analog and digital sensor systems, data loggers, etc. that require connectivity to
various USB hosts.
Family members available are summarized in Table 1.
Table 1. Family Members
Device
MSP430F5529
MSP430F5528
MSP430F5527
MSP430F5526
MSP430F5525
MSP430F5524
MSP430F5522
MSP430F5521
MSP430F5519
MSP430F5517
MSP430F5515
MSP430F5514
MSP430F5513
Flash
(KB)
128
128
96
96
64
64
32
32
128
96
64
64
32
USCI
SRAM
(KB) ⁽¹⁾
Timer_A ⁽²⁾
Timer_B^{(3) Channel A: Channel B:}
UART/IrDA/ SPI/I²C
ADC12_A
(Ch)
Comp_B
(Ch)
I/O
Package
Type
SPI
8+2
5, 3, 3
7
2
2
14 ext / 2 int
12
63
80 PN
8+2
5, 3, 3
7
2
2
10 ext / 2 int
8
47
64 RGC,
80 ZQE
6+2
5, 3, 3
7
2
2
14 ext / 2 int
12
63
80 PN
6+2
5, 3, 3
7
2
2
10 ext / 2 int
8
47
64 RGC,
80 ZQE
4+2
5, 3, 3
7
2
2
14 ext / 2 int
12
63
80 PN
4+2
5, 3, 3
7
2
2
10 ext / 2 int
8
47
64 RGC,
80 ZQE
8+2
5, 3, 3
7
2
2
10 ext / 2 int
8
47
64 RGC,
80 ZQE
6+2
5, 3, 3
7
2
2
14 ext/ 2 int
12
63
80 PN
8+2
5, 3, 3
7
2
2
-
12
63
80 PN
6+2
5, 3, 3
7
2
2
-
12
63
80 PN
4+2
5, 3, 3
7
2
2
-
12
63
80 PN
4+2
5, 3, 3
7
2
2
-
8
47
64 RGC,
80 ZQE
4+2
5, 3, 3
7
2
2
-
8
47
64 RGC,
80 ZQE
(1) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.
(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(3) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
2
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