MSP430F551X_1 Datasheet, PDF (19/115 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F551x
MSP430F552x
www.ti.com
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
System Reset
Power-Up
External Reset
Watchdog Timeout, Password
Violation
Flash Memory Password Violation
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
Comp_B
TB0
TB0
Watchdog Timer_A Interval Timer
Mode
USCI_A0 Receive/Transmit
USCI_B0 Receive/Transmit
ADC12_A
TA0
TA0
USB_UBM
DMA
TA1
TA1
I/O Port P1
USCI_A1 Receive/Transmit
USCI_B1 Receive/Transmit
TA2
TA2
I/O Port P2
RTC_A
WDTIFG, KEYV (SYSRSTIV)^{(1) (2)}
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV)⁽¹⁾
NMIIFG, OFIFG, ACCVIFG, BUSIFG
(SYSUNIV)^{(1) (2)}
Comparator B interrupt flags (CBIV)^{(1) (3)}
TB0CCR0 CCIFG0 ⁽³⁾
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV)^{(1) (3)}
WDTIFG
UCA0RXIFG, UCA0TXIFG (UCA0IV)^{(1) (3)}
UCB0RXIFG, UCB0TXIFG (UCAB0IV)^{(1) (3)}
ADC12IFG0 to ADC12IFG15 (ADC12IV)^{(1) (3) (4)}
TA0CCR0 CCIFG0⁽³⁾
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)^{(1) (3)}
USB interrupts (USBIV)^{(1) (3)}
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)^{(1) (3)}
TA1CCR0 CCIFG0⁽³⁾
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)^{(1) (3)}
P1IFG.0 to P1IFG.7 (P1IV)^{(1) (3)}
UCA1RXIFG, UCA1TXIFG (UCA1IV)^{(1) (3)}
UCB1RXIFG, UCB1TXIFG (UCB1IV)^{(1) (3)}
TA2CCR0 CCIFG0⁽³⁾
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)^{(1) (3)}
P2IFG.0 to P2IFG.7 (P2IV)^{(1) (3)}
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV)^{(1) (3)}
Reserved
Reserved ⁽⁵⁾
SYSTEM
INTERRUPT
Reset
(Non)maskable
(Non)maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
WORD
ADDRESS
PRIORITY
0FFFEh
63, highest
0FFFCh
62
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
0FFEAh
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
0FFDEh
0FFDCh
0FFDAh
0FFD8h
0FFD6h
0FFD4h
0FFD2h
0FFD0h
⋮
0FF80h
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
⋮
0, lowest
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Only on devices with ADC, otherwise reserved.
(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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