CC2564_15 Datasheet, PDF (19/47 Pages) Texas Instruments – Bluetooth® and Dual-Mode Controller

CC256x
www.ti.com
SWRS121D – JULY 2012 – REVISED JANUARY 2014
• Clk_Idle_Start: indicates the number of clock cycles from the beginning of the frame to the beginning of
the idle period. After Clk_Idle_Start clock cycles, the clock becomes 0.
• Clk_Idle_End: indicates the time from the beginning of the frame to the end of the idle period. The time
is given in multiples of clock periods.
The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period.
For example, for clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90.
Between both Frame_Sync signals there are 70 clock cycles (instead of 100). The clock idle period starts
60 clock cycles after the beginning of the frame and lasts 90 – 60 = 30 clock cycles. Thus, the idle period
ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end before the
beginning of the idle period.
Figure 3-13 shows the frame idle timing.
Frame_Sync
Frame period
Data_In
Data_Out
Clock
Frame idle
Clk_Idle_Start
Clk_Idle_End
Figure 3-13. Frame Idle Period
frmidle_swrs064
3.5.3.5 Clock-Edge Operation
The codec interface of the device can work on the rising or the falling edge of the clock and can sample
the Frame_Sync signal and the data at inversed polarity.
Figure 3-14 shows the operation of a falling-edge-clock type of codec. The codec is the master of the bus.
The Frame_Sync signal is updated (by the codec) on the falling edge of the clock and is therefore
sampled (by the device) on the next rising clock. The data from the codec is sampled (by the device) on
the falling edge of the clock.
PCM FSYNC
PCM CLK
PCM DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
CC256x
SAMPLE TIME
Figure 3-14. Negative Clock Edge Operation
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
SWRS121-004
Detailed Description
19