CC2564_15 Datasheet, PDF (15/47 Pages) Texas Instruments – Bluetooth® and Dual-Mode Controller

CC256x
www.ti.com
SWRS121D – JULY 2012 – REVISED JANUARY 2014
3.5 Functional Blocks
The CC256x architecture comprises a DRP™ and a point-to-multipoint baseband core. The architecture is
based on a single-processor ARM7TDMIE^® core. The device includes several on-chip peripherals to
enable easy communication with a host system and the Bluetooth BR/EDR/LE core.
3.5.1 RF
The device is the third generation of TI Bluetooth single-chip devices using DRP architecture.
Modifications and new features added to the DRP further improve radio performance.
Figure 3-10 shows the DRP block diagram.
TX digital data
Digital
Transmitter path
Amplitude
Phase
ADPLL
DPA
Receiver path
RX digital data
Demodulation
ADC
IFA
Filter
LNA
Figure 3-10. DRP Block Diagram
SWRS092-005
3.5.1.1 Receiver
The receiver uses near-zero-IF architecture to convert the RF signal to baseband data. The signal
received from the external antenna is input to a single-ended low-noise amplifier (LNA) and passed to a
mixer that downconverts the signal to IF, followed by a filter and amplifier. The signal is then quantized by
a sigma-delta analog-to-digital converter (ADC) and further processed to reduce the interference level.
The demodulator digitally downconverts the signal to zero-IF and recovers the data stream using an
adaptive-decision mechanism. The demodulator includes EDR processing with:
• State-of-the-art performance
• A maximum-likelihood sequence estimator (MLSE) to improve the performance of basic-rate GFSK
sensitivity
• Adaptive equalization to enhance EDR modulation
New features include:
• LNA input range narrowed to increase blocking performance
• Active spur cancellation to increase robustness to spurs
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