71M6531D Datasheet, PDF (88/115 Pages) Teridian Semiconductor Corporation – Energy Meter IC

Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
The CE is initialized and its functions are controlled by the MPU using CECONFIG. This register contains
in packed form SAG_CNT, FREQSEL, EXT_PULSE, I0_SHUNT, I1_SHUNT, PULSE_SLOW and PULSE_FAST.
The CECONFIG bit definitions are given in Table 52.
CE Address
0x20
Name
CECONFIG
Data
0x5020
Description
See description of the CECONFIG bits in Table 52.
IA_SHUNT and/or IB_SHUNT can configure their respective current inputs to accept shunt resistor sen-
sors. In this case the CE provides an additional gain of 8 to the selected current input. WRATE may need
to be adjusted based on the values of IA_SHUNT and IB_SHUNT. Whenever IA_SHUNT or IB_SHUNT are
set to 1, In_8 (in the equation for Kh) is assigned a value of 8.
The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control
is by the MPU if EXT_PULSE = 1. In this case, the MPU controls the pulse rate by placing values into
APULSEW, APULSER, APULSE2 and APULSE3. By setting EXT_PULSE = 0, the CE controls the pulse rate
based on W0SUM_X and VAR0SUM_X (EQU = 0) or WSUM_X (EQU = 2).
If EXT_PULSE = 1 and EQU = 2, the pulse inputs are W0SUM_X + W1SUM_X and VAR0SUM_X +
VAR1SUM_X. In this case, creep cannot be controlled since creep is an MPU function.
If EXT_PULSE = 1 and EQU = 0, the pulse inputs are W0SUM_X if I0SQSUM_X > I1SQSUM_X and
W1SUM_X, if I1SQSUM_X > I0SQSUM_X.
The 71M6531 Demo Code creep function halts both internal and external pulse generation.
The EXT_TEMP bit controls the temperature compensation mode:
• When EXT_TEMP = 0 (internal compensation), the CE will control the gain using GAIN_ADJ (see Table 54)
based on PPMC, PPMC2 and TEMP_X, the difference between die temperature and the refer-
ence/calibration temperature TEMP_NOM. Since PPMC and PPMC2 reflect the typical behavior of the
reference voltage over temperature, the internal temperature compensation eliminates the effects of
temperature-related errors of VREF only.
• When EXT_TEMP = 1 (external compensation), the MPU is allowed to control the CE gain using
GAIN_ADJ, based on any algorithm implemented in MPU code.
The FREQSEL1 and FREQSEL0 bits select the phase used to control the CE-internal PLL. CE accuracy
depends on the channel selected by the FREQSEL1 and FREQSEL0 bits receiving a clean voltage signal.
Table 52: CECONFIG Bit Definitions
CECONFIG
[bit]
[19]
[18]
[17]
Name
SAG_MASK1
SAG_MASK0
SAG_INT
[16]
EXT_TEMP
[15:8]
SAG_CNT
[7]
FREQSEL1
[6]
FREQSEL0
Default
Description
0
0
0
0
80
(0x50)
0
0
Sets the sag control of phase B.
Sets the sag control of phase A.
When set, enables the sag interrupt to be output on the
YPULSE pin.
When set, enables the control of GAIN_ADJ by the MPU.
When 0, enables the control of GAIN_ADJ by the CE.
The number of consecutive voltage samples below SAG_THR
before a sag alarm is declared. The maximum value is 255.
SAG_THR is at address 0x24.
Selects the phase to be used for the frequency monitor.
FREQSEL1/FREQSEL0 = 0/0: Phase A
FREQSEL1/FREQSEL0 = 0/1: Phase B
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