71M6531D Datasheet, PDF(6/115 Page) Teridian Semiconductor Corporation

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71M6531D Datasheet, PDF (6/115 Pages) Teridian Semiconductor Corporation – Energy Meter IC

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Data Sheet 71M6531D/F-71M6532D/F

FDS 6531/6532 005

Figure 50: LQFP-100 Package, Mechanical Drawing............................................................................... 109

Figure 51: I/O Equivalent Circuits ............................................................................................................. 112

Tables

Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ....................................................... 11

Table 2: ADC Resolution............................................................................................................................. 12

Table 3: ADC RAM Locations ..................................................................................................................... 12

Table 4: XRAM Locations for ADC Results ................................................................................................ 15

Table 5: Meter Equations ............................................................................................................................ 16

Table 6: CKMPU Clock Frequencies .......................................................................................................... 19

Table 7: Memory Map ................................................................................................................................. 20

Table 8: Internal Data Memory Map ........................................................................................................... 21

Table 9: Special Function Register Map ..................................................................................................... 22

Table 10: Generic 80515 SFRs - Location and Reset Values .................................................................... 22

Table 11: PSW Bit Functions (SFR 0xD0) ................................................................................................... 23

Table 12: Port Registers ............................................................................................................................. 24

Table 13: Stretch Memory Cycle Width ...................................................................................................... 25

Table 14: 71M6531D/F and 71M6532D/F Specific SFRs........................................................................... 25

Table 15: Baud Rate Generation ................................................................................................................ 27

Table 16: UART Modes............................................................................................................................... 27

Table 17: The S0CON (UART0) Register (SFR 0x98)................................................................................. 28

Table 18: The S1CON (UART1) register (SFR 0x9B).................................................................................. 28

Table 19: PCON Register Bit Description (SFR 0x87) ................................................................................ 28

Table 20: Timers/Counters Mode Description ............................................................................................ 29

Table 21: Allowed Timer/Counter Mode Combinations .............................................................................. 29

Table 22: TMOD Register Bit Description (SFR 0x89)................................................................................ 30

Table 23: The TCON Register Bit Functions (SFR 0x88)............................................................................ 30

Table 24: The IEN0 Bit Functions (SFR 0xA8)............................................................................................ 31

Table 25: The IEN1 Bit Functions (SFR 0xB8)............................................................................................ 31

Table 26: The IEN2 Bit Functions (SFR 0x9A)............................................................................................ 31

Table 27: TCON Bit Functions (SFR 0x88) ................................................................................................. 32

Table 28: The T2CON Bit Functions (SFR 0xC8)........................................................................................ 32

Table 29: The IRCON Bit Functions (SFR 0xC0) ........................................................................................ 32

Table 30: External MPU Interrupts.............................................................................................................. 33

Table 31: Interrupt Enable and Flag Bits .................................................................................................... 33

Table 32: Interrupt Priority Level Groups .................................................................................................... 34

Table 33: Interrupt Priority Levels ............................................................................................................... 34

Table 34: Interrupt Priority Registers (IP0 and IP1) .................................................................................... 34

Table 35: Interrupt Polling Sequence.......................................................................................................... 35

Table 36: Interrupt Vectors.......................................................................................................................... 35

Table 37: Clock System Summary.............................................................................................................. 37

Table 38: Bank Switching with FL_BANK[2:0] ............................................................................................ 40

Table 39: Data/Direction Registers and Internal Resources for DIO Pins (71M6531D/F) ......................... 42

Table 40: Data/Direction Registers and Internal Resources for DIO Pins (71M6532D/F) ......................... 44

Table 41: DIO_DIR Control Bit .................................................................................................................... 45

Table 42: Selectable Controls using the DIO_DIR Bits ............................................................................... 45

Table 43: EECTRL Bits for 2-pin Interface................................................................................................... 47

Table 44: EECTRL Bits for the 3-Wire Interface .......................................................................................... 48

Table 45: SPI Command Description.......................................................................................................... 50

v1.2

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