71M6531D Datasheet, PDF(29/115 Page) Teridian Semiconductor Corporation

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71M6531D Datasheet, PDF (29/115 Pages) Teridian Semiconductor Corporation – Energy Meter IC

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FDS 6531/6532 005

Data Sheet 71M6531D/F-71M6532D/F

1.4.7 Timers and Counters

The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be con-

figured for counter or timer operations.

In timer mode, the register is incremented every machine cycle, i.e. it counts up once for every 12 periods

of the MPU clock. In counter mode, the register is incremented when the falling edge is observed at the

corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins,

see Section 1.5.7 Digital I/O). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum

input count rate is 1/2 of the clock frequency (CKMPU). There are no restrictions on the duty cycle, how-

ever to ensure proper recognition of the 0 or 1 state, an input should be stable for at least 1 machine

cycle.

Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 20 and Table 21. The

TMOD Register, shown in Table 22, is used to select the appropriate mode. The timer/counter operation

is controlled by the TCON Register, which is shown in Table 23. Bits TR1 (TCON[6]) and TR0 (TCON[4]) in

the TCON register start their associated timers when set.

Table 20: Timers/Counters Mode Description

Mode

Function

Mode 0 13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 register and

the remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1,

respectively). The 3 high order bits of TL0 and TL1 are held at zero.

Mode 1 16-bit Counter/Timer mode.

Mode 2 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1,

while TL0 or TL1 is incremented every machine cycle. When TL(x) over-

flows, a value from TH(x) is copied to TL(x) (where x is 0 for coun-

ter/timer 0 or 1 for counter/timer 1.

Mode

Function

Mode 3 If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.

If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent

8-bit Timer/Counters.

In Mode 3, TL0 is affected by TR0 and gate control bits and sets the TF0 flag on overflow, while TH0

is affected by the TR1 bit and the TF1 flag is set on overflow.

Table 21 specifies the combinations of operation modes allowed for Timer 0 and Timer 1.

Table 21: Allowed Timer/Counter Mode Combinations

Timer 0 - mode 0

Timer 0 - mode 1

Timer 0 - mode 2

Mode 0

YES

Not allowed

Timer 1

Mode 1

YES

Not allowed

Mode 2

YES

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