71M6531D Datasheet, PDF (78/115 Pages) Teridian Semiconductor Corporation – Energy Meter IC

Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Name
FLSH_ERASE
[7:0]
FLSH_MEEN
FLSH_PGADR
[5:0]
FLSH_PWE
GP0
…
GP7
IE_FWCOL0
IE_FWCOL1
IE_PB
IE_PLLRISE
IE_PLLFALL
IEN_SPI
78
Location Reset Wake Dir
Description
SFR 94[7:0] 0
0
W Flash Erase Initiate. (Default = 0x00). FLSH_ERASE is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle.
0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR @ SFR 0xB7.
0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be enabled.
Any other pattern written to FLSH_ERASE will have no effect. The erase cycle is not
completed until 0x00 is written to FLSH_ERASE.
SFR B2[1]
0
0
W Mass Erase Enable.
0 = Mass Erase disabled (default).
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
SFR B7 [7:2] 0
0
W Flash Page Erase Address. (Default = 0x00)
FLSH_PGADR[5:0] with FL_BANK[2:0], sets the Flash Page Address (page 0 through
127) that will be erased during the Page Erase cycle.
Must be re-written for each new Page Erase cycle.
SFR B2[0]
0
0 R/W Program Write Enable. This bit must be cleared by the MPU after each byte write op-
eration. Write operations to this bit are inhibited when interrupts are enabled.
0 = MOVX commands refer to XRAM Space, normal operation (default).
1 = MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
20C0
…
20C7
0
NV R/W Non-volatile general-purpose registers powered by the RTC supply. These registers
…
…
maintain their value in all power modes, but will be cleared on reset. The values of
0
NV
GP0…GP7 will be undefined if VBAT drops below the minimum value.
SFR E8[2]
0
SFR E8[3]
0
SFR E8[4]
0
SFR E8[6]
0
0 R/W Interrupt flags for Firmware Collision Interrupt. See the Flash Memory section for de-
0 R/W ^tails.
– R/W PB flag. Indicates that a rising edge occurred on PB. Firmware must write a zero to
this bit to clear it. The bit is also cleared when the MPU requests SLEEP or LCD
mode. On bootup, the MPU can read this bit to determine if the part was woken with
the PB (DIO0[0]).
0 R/W Indicates that the MPU was woken or interrupted (INT4) by system power becoming
available, or more precisely, by PLL_OK rising. The firmware must write a zero to this
bit to clear it.
SFR E8[7]
0
0 R/W Indicates that the MPU has entered BROWNOUT mode because system power has
become unavailable (INT4), or more precisely, because PLL_OK fell. This bit will not
be set if the part wakes into BROWNOUT mode because of PB or the WAKE timer.
The firmware must write a zero to this bit to clear it.
20B0[4]
0
– R/W SPI interrupt enable.
© 2005-2009 TERIDIAN Semiconductor Corporation
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