71M6531D Datasheet, PDF (77/115 Pages) Teridian Semiconductor Corporation – Energy Meter IC

FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Name
DIO_EEX[1:0]
DIO_PV
DIO_PW
DIO_PX
DIO_PY
EEDATA[7:0]
EECTRL[7:0]
ECK_DIS
Location
2008[7:6]
2008[2]
2008[3]
200F[3]
200F[2]
SFR 9E
SFR 9F
2005[5]
Reset Wake Dir
Description
0
0 R/W When set, converts DIO4 and DIO5 to interface with external EEPROM. DIO4 be-
comes SDCK and DIO5 becomes bi-directional SDATA.
DIO_EEX[1:0]
00
01
10
11
Function
Disable EEPROM interface
2-Wire EEPROM interface
3-Wire EEPROM interface
not used
0
0 R/W Causes VARPULSE to be output on DIO7.
0
0 R/W Causes WPULSE to be output on DIO6.
0
0 R/W Causes XPULSE to be output on DIO8.
0
0 R/W Causes YPULSE to be output on DIO9.
0
0 R/W Serial EEPROM interface data.
0
0 R/W Serial EEPROM interface control.
0
0 R/W Emulator clock disable. When ECK_DIS = 1, the emulator clock is disabled.
If ECK_DIS is set, the emulator and programming devices will be unable to
erase or program the device.
EQU[2:0]
2000[7:5]
0
EX_XFR
2002[0]
0
EX_RTC
2002[1]
0
EX_FWCOL
2007[4]
0
EX_PLL
2007[5]
0
FIR_LEN[1:0] 2007[3:2]
1
FL_BANK[2:0] SFR B6[2:0] 1
0 R/W Specifies the power equation to be used by the CE.
0 R/W Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, the Firm-
0
WareCollision (FWCOL) and PLL interrupts. Note that if one of these interrupts is to
0
be enabled, its corresponding MPU EX enable must also be set. See Section 1.4.9
0
Interrupts for details.
1 R/W FIR_LEN[1:0] controls the length of the ADC decimation FIR filter and therefore con-
trols the time taken for each conversion.
[M40MHZ, M26MHZ]
FIR_LEN
Resulting FIR
Filter Cycles
Resulting Resulting
CK32 Cycles DC Gain
[00], [10], or [11]
00
138
1
0.110017
01
288
2
1.000
10
384
3
2.37037
[01]
00
186
1
0.113644
01
384
2
1.000
10
588
3
3.590363
1 R/W Flash bank. Memory above 32 KB is mapped to the MPU address space from 0x8000
to 0xFFFF in 32 KB banks. When MPU address[15] = 1, the address in flash is
mapped to FL_BANK[2:0], MPU Address[14:0]. FL_BANK is reset by the erase cycle.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
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