71M6531D Datasheet, PDF (33/115 Pages) Teridian Semiconductor Corporation – Energy Meter IC

FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
The 71M6531D/F and 71M6532D/F MPU allows seven external interrupts. These are connected as
shown in Table 30. The polarity of interrupts 2 and 3 is programmable in the MPU via the I3FR and I2FR
bits in T2CON. Interrupts 2 and 3 should be programmed for falling sensitivity (I3FR = I2FR = 0). The ge-
neric 8051 MPU literature states that interrupts 4 through 6 are defined as rising-edge sensitive. Thus,
the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in
Table 30.
Table 30: External MPU Interrupts
External
Interrupt
0
1
2
3
4
5
6
Connection
Digital I/O High Priority
Digital I/O Low Priority
FWCOL0, FWCOL1, SPI
CE_BUSY
PLL_OK (rising), PLL_OK (falling)
EEPROM busy
XFER_BUSY, RTC_1SEC or WD_NROVF
Polarity
see Section 1.5.7
see Section 1.5.7
falling
falling
rising
falling
falling
Flag Reset
automatic
automatic
automatic
automatic
automatic
automatic
manual
External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See Section
1.5.7 Digital I/O for more information.
FWCOLx interrupts occur when the CE collides with a flash write attempt. See the flash write description
in the Flash Memory section for more detail.
SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its
own flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler.
XFER_BUSY, RTC_1SEC, WD_NROVF, FWCOL0, FWCOL1, SPI, PLLRISE and PLLFALL have their
own enable and flag bits in addition to the interrupt 6, 4 and enable and flag bits (see Table 31).
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other
flags, IE_XFER through IE_PB, are cleared by writing a zero to them.
Since these bits are in an SFR bit addressable byte, common practice would be to clear them
with a bit operation, but this must be avoided. The hardware implements bit operations as a
byte-wide read-modify-write hardware macro. If an interrupt occurs after the read, but before
the write, its flag will be cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a zero in the
location of the bit to be cleared. The flag bits are configured in hardware to ignore ones written to them.
Table 31: Interrupt Enable and Flag Bits
Interrupt Enable
Name
Location
EX0
SFR A8[0]
EX1
SFR A8[2]
EX2
SFR B8[1]
EX3
SFR B8[2]
EX4
SFR B8[3]
EX5
SFR B8[4]
EX6
SFR B8[5]
EX_XFER
2002[0]
EX_RTC
2002[1]
IEN_WD_NROVF 20B0[0]
IEN_SPI
20B0[4]
EX_FWCOL
2007[4]
Interrupt Flag
Name
Location
IE0
SFR 88[1]
IE1
SFR 88[3]
IEX2
SFR C0[1]
IEX3
SFR C0[2]
IEX4
SFR C0[3]
IEX5
SFR C0[4]
IEX6
SFR C0[5]
IE_XFER
SFR E8[0]
IE_RTC
SFR E8[1]
WD_NROVF_FLAG 20B1[0]
SPI_FLAG
20B1[4]
IE_FWCOL0
SFR E8[3]
Interrupt Description
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (INT 6)
RTC_1SEC interrupt (INT 6)
WDT near overflow (INT 6)
SPI Interface (INT2)
FWCOL0 interrupt (INT 2)
v1.2
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