71M6515H_11 Datasheet, PDF (59/60 Pages) Teridian Semiconductor Corporation – Up to 10ppmC precision ultra-stable voltage reference Digital temperature compensation

71M6515H
A Maxim Integrated Products Brand
Energy Meter IC
DATA SHEET
JULY 2011
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Date
October 26, 2005
December 11, 2006
March 15, 2007
August 17, 2007
March 5, 2008
Description
First publication.
Changed capacitor values for XIN/XOUT
Corrected addresses for CE_DATA and made addresses CE_DATA etc. visible in
table “Registers in Numerical Order”.
Changed frequency range to 46-64Hz and “Real-time clock for TOU” to “Real-time
clock with temperature compensation” on title page.
Added complete chapter on communication between host and 6515H.
Changed pin name V1 to VFLT in Electrical Specification.
Consolidated spelling for CREEP_THRSLD register. Added explanation for X in
formula for WRATE.
Added information on processing time for registers involving post-processing.
Changed default value for WRATE to 683.
Deleted note on low-pass filter in the CE in CONFIG register description.
Added note at CONFIG register description stating that phase with stable voltage
can be selected with F_SELECT to avoid inaccurate measurements and note
stating that PULSE_SLOW and PULSE_FAST affect all four pulse sources.
Added diagram “Connections between 71M6515H and host”.
Added I/O Equivalent Circuit diagrams and circuit type numbers in Pin Descriptions.
Added note in Pin Descriptions stating that the voltage at RX must not exceed 3.6V.
Added VREF aging data.
Clarified polarity of SSDAT and SSCLK pins.
Changed recommended value for capacitors at XIN/XOUT to 22pF.
Changed recommended crystal to ECS ECX-3TA series.
Added note on exact length of default accumulation interval.
Corrected bit locations for D_CONFIG register.
Added note in pin description for D0-D7 and Digital I/O” section: D0 through D7 are
high impedance after reset or power-up and are configured as outputs and driven
low 140ms after RESETZ goes high.
Updated default values for VIPTHRESH and VI_THRESH.
Changed pin and register names to PULSEW and PULSER and updated block
diagram (Figure 2), updated pin-out diagram with corrected pin names.
Removed COMPARATOR table in ELECTRICAL SPECIFICATIONS.
Changed note for SRDY in pin description table to “SRDY should be tied to ground”,
deleted Figure 13 (SRDY function) and removed all text describing the function of
SRDY (except that SRDY should be grounded), deleted Figure 13 (SSI Timing w/
SRDY) and removed references to SRDY in Figure 12.
Consolidated spelling of Y_CALC etc. constants in section “Temperature Com-
pensation for the Crystal and RTC” and in the register tables.
Added reference to fast calibration procedure (AN_651X_022).
Added diagrams for metering configurations.
Improved Table 6 and explanation of PULSE_SRC register.
Changed capacitor values for XIN/XOUT to 27pF and added recommended load
capacitance value (12.5pF).
Changed register name at location 0x38 from QUANT_V to QUANT_I.
Removed non lead-free packages from Ordering Information.
Updated Teridian street address.
Added text at explanation of bits 14-12 of the STATUS register stating that these bits
are also set when the current is below the threshold defined by bits 15-0 of the
START_THRESHLD register. Added at explanation of START_THRESHLD : “Elements
with VRMS< V_START will not set the creep bits in the STATUS register” and
“Elements with ISQSUM< I_START will set the creep bits in the STATUS register”.
Page: 59 of 60
© 2005−2011 Teridian Semiconductor Corporation
1.6