71M6515H_11 Datasheet, PDF (42/60 Pages) Teridian Semiconductor Corporation – Up to 10ppmC precision ultra-stable voltage reference Digital temperature compensation

71M6515H
A Maxim Integrated Products Brand
Energy Meter IC
DATA SHEET
JULY 2011
The 71M6515H performs ADC temperature compensation by computing a gain adjustment factor for both the voltage and
current samples per the following equation:
GAIN_ADJ=16384+floor(1+DELTA_T*PPMC/2¹⁴+DELTA_T²*PPMC2/2²³)
Changes to PPMC1_2 by the host are only allowed if the DEFAULT_PPM bit in the CONFIG register is zero. If additional
temperature compensation by the host, e.g. for external components, is required, the procedure is as follows:
1) The host sets the DEFAULT_PPM bit in the CONFIG register to 1 and then reads PPMC and PPMC2.
2) The host then adds the compensation factors to PPMC and PPMC2, resets the DEFAULT_PPM bit in the CONFIG
register to 0 and then writes the modified values to PPMC and PPMC2.
Y_DEG0 (0x18)
This register holds the constant compensation factor for the RTC temperature compensation. One LSB is equivalent to
0.1PPM.
Bits 31-16: These bits (Y_CALC0) represent the constant compensation factor.
Y_DEG1_2 (0x19)
This register holds the linear and quadratic compensation factors for the RTC temperature compensation.
31
16 15
0
Y_CALC1 = linear compensation factor. One LSB is equi- Y_CALC2 = quadratic compensation factor. One LSB is
valent to 0.01PPM/°
equivalent to 0.001PPM/°C
Both Y_DEG0 and Y_DEG1_2 can be used to compensate the RTC to be accurate over the whole temperature range by
characterizing the crystal.
Registers for Output Signals
PULSEW_R_CNTS (0x41)
This register contains the pulse count for the PULSEW and PULSER output pins for the past accumulation interval. The
counters will be cleared at the beginning of each accumulation interval and then start counting up with each generated pulse.
Bit 15-0: The counter for the PULSER (VARh) generator.
Bit 31-16: The counter for the PULSEW (Wh) generator.
31
Counter for the PULSEW generator (Wh)
16 15
0
Counter for the PULSER generator (VARh)
At pulse rates that do not result in generation of whole counts per accumulation interval, e.g. 3 1/3 pulses, the count equivalent
to the next lower natural number will be generated until the residue accumulates to a full count, i.e. the pulse sequence
generated will be 3, 3, 3, 4, 3, 3, 3, 4…
PULSE3_4_CNTS (0x42)
This register contains the pulse count for the PULSE3 and PULSE4 output pins for the accumulation interval. The counters
will be cleared at the beginning of each accumulation interval and then start counting up with each generated pulse.
Bit 15-0: The counter for the PULSE4 generator.
Bit 31-16: The counter for the PULSE3 generator.
31
16 15
0
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