71M6515H_11 Datasheet, PDF (39/60 Pages) Teridian Semiconductor Corporation – Up to 10ppmC precision ultra-stable voltage reference Digital temperature compensation

71M6515H
A Maxim Integrated Products Brand
Energy Meter IC
DATA SHEET
JULY 2011
Bits 20-19: These two bits (F_SELECT) select the phase that is to be used for frequency measurement. The frequency will
be shown in bits 31-16 of the FREQ_DELTA_T register (and as bit 4 of the STATUS word – in this form as a digitized zero
crossing signal).
Bit 20
F_SELECT1
0
0
1
1
Bit 19
F_SELECT0
0
1
0
1
F_SELECT
0
1
2
3
Phase
Selected
Phase A
Phase B
Phase C
Not allowed
Since the signal at the input selected with F_SELECT is used to synchronize filters and other processing stages in the CE,
accuracy for most measurements will be reduced if no voltage is present at the selected phase input. Accuracy can be
established by selecting the phase that carries a stable signal (A, B, or C).
Bit 21: This bit (CE_ONLY) disables the post-processor when set to 1. When the post-processor is disabled, the time-
intensive computations of IPHASE, IRMS, VAh and VRMS are not performed, and therefore smaller accumulation times
(SUM_CYCLES < 24) are permitted. In this case, the host is responsible for calculating IPHASE, IRMS, VAh and VRMS.
Bits 23-22: These two bits (IMAGE) select the code to be used by the CE. The CE can be operated in standard mode
when using CTs and/or shunt resistor sensors or in Rogowski mode when using Rogowski coil sensors. In order to switch
the operation mode, the CE has to be disabled first by clearing the CE_EN bit.
Bit 23
IMAGE 1
0
0
1
1
Bit 22
IMAGE 0
0
1
0
1
IMAGE
0
1
2
3
CE Code Selected
Standard (CT/shunt)
Rogowski coil
Standard (CT/shunt)
Standard (CT/shunt)
Bit 24: This bit (RESET), when reset, forces all internal states of the 71M6515H to their power-up default.
Bits 26-25: These two bits (PULSE_SLOW, PULSE_FAST) modify the speed of the pulse generator. PULSE_SLOW and
PULSE_FAST determine the factor X in the equation used for Kh as shown in the table below.
PULSE_SLOW
0
0
1
1 (default)
PULSE_FAST
0
1
0
1 (default)
X
1.5*2² = 6
1.5*2⁶ = 96
1.5*2^-4 = 0.09375
1.5
PULSE_SLOW and PULSE_FAST will affect the operation of all four pulse outputs. See the Pulse Generation section for
details.
Bits 29-27: These three bits (IA_8X, IB_8X, IC_8X) apply an additional gain of 8 to the IA, IB, and IC channels when set to
1. This is a useful tool when very small signals are encountered, as is the case when using current shunt resistors with
very low resistance while operating at low currents. Care must be taken to avoid clipping. If the input to the meter exceeds
IMAX/8, clipping will occur. These bits should normally be zero, unless additional gain following the ADC stage is needed.
Bit 30: This bit (DEFAULT_PPM) defines the source of temperature compensation. When DEFAULT_PPM is 1, the
71M6515H will automatically apply compensation coefficients derived from the stored VREF temperature characteristics to
the PPMC and PPMC2 registers. When DEFAULT_PPM is zero, the host is allowed to write its own values to the PPMC and
PPMC2 registers.
Page: 39 of 60
© 2005−2011 Teridian Semiconductor Corporation
1.6