71M6515H_11 Datasheet, PDF (40/60 Pages) Teridian Semiconductor Corporation – Up to 10ppmC precision ultra-stable voltage reference Digital temperature compensation

71M6515H
A Maxim Integrated Products Brand
Energy Meter IC
DATA SHEET
JULY 2011
STATUS (0x14)
The four bytes in this register reflect the status of the various measurement functions of the 71M6515H. This register is
read only. When a bit in the STMASK register is set, an interrupt (IRQZ) is generated as soon as the corresponding bit in
the STATUS register is set.
Bit 0: This bit (BOOTUP) signals a request from the 71M6515H to the host to be initialized.
Bit 1: This bit (SAGA ), when set, indicates that the voltage applied to phase A has sagged below SAGTHR. See the for SAG
register for a detailed description.
Bit 2: This bit (SAGB), when set, indicates that the voltage applied to phase B has sagged below SAGTHR.
Bit 3: This bit (SAGC), when set, indicates that the voltage applied to phase C has sagged below SAGTHR.
Bit 4: This bit (F0) follows the polarity of the input voltage selected with the F_SELECT bits in the CONFIG register. It
represents a smoothed, filtered and squared copy of the fundamental waveform.
Bit 5: This bit (MAXV), when set, indicates that a voltage greater than the voltage limit defined in the VI_PTHRESHOLD
register had been detected in the previous accumulation interval.
Bit 6: This bit (MAXI), when set, indicates that a current greater than the current limit defined in the VI_PTHRESHOLD
register had been detected in the previous accumulation interval.
Bit 7: This bit (1SECI, toggles every second. It is controlled by the RTC.
Bit 8: This bit (VXEDGE), when set, indicates a change in state of VX comparator. This bit is updated every accumulation
interval.
Bit 9: This bit (DEDGE), when set, indicates a change in state of any selected DIO pin. This bit is updated every
accumulation interval. Pins have to be configured to generate the DEDGE flag using the DIO_INT_CTRL bits in the
D_CONFIG register.
Bit 10: This bit (XOVF), when set, indicates that the host failed to read at least one of the Wh values. Between interrupts
(indicated by the READY bit in the STATUS word), the 71M6515H expects the host to read at least one of the WATTHR_A,
WATTHR_B, or WATTHR_C values.
Bit 11: This bit (READY), when set, indicates that the 71M6515H has fresh output values ready for the host. Setting this bit
in STMASK will enable the hardware interrupt output pin IRQZ.
Bit 14-12: These bits (bit 12 for phase A, bit 13 for phase B, bit 14 for phase C), when set, indicate that the energy
received from element A, B, or C is below the creep threshold defined in the CREEP_THRSHLD register or that the current
in elements A, B, or C is below the threshold defined in bits 15-0 of the START_THRESHLD register. The creep condition
flagged by bits 14-12 of the STATUS register indicates that Wh, VARh, and IRMS measurements of element A, B, or C
have been zeroed out. Consequently, accumulation did not occur.
Bit 15: This bit (CMD_IGNORED), when set, indicates that the 71M6515H ignored the last command received from the
host. The reason can be any type of command incompatibility, e.g. attempts to write to a read-only register.
Bit 16: This bit (PULSEW_ERR), when set, indicates that the pulse generator PULSEW is configured for external (host)
input, but did not receive an update during the previous accumulation interval.
Bit 17: This bit (PULSER_ERR), when set, indicates that the pulse generator PULSER is configured for external (host) input,
but did not receive an update during the previous accumulation interval.
Bit 18: This bit (PULSE3_ERR), when set, indicates that the pulse generator PULSE3 is configured for external (host) input,
but did not receive an update during the previous accumulation interval.
Bit 19: This bit (PULSE4_ERR), when set, indicates that the pulse generator PULSE4 is configured for external (host) input,
but did not receive an update during the previous accumulation interval.
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