71M6515H_11 Datasheet, PDF (55/60 Pages) Teridian Semiconductor Corporation – Up to 10ppmC precision ultra-stable voltage reference Digital temperature compensation

71M6515H
A Maxim Integrated Products Brand
Energy Meter IC
DATA SHEET
JULY 2011
flag in the STATUS register. This happens because the incomplete or garbled data could have included a write command to the
CONFIG register or other important registers.
Methods of Control
Two different methods of control can be used by the host processor:
1) Synchronization using the IRQZ pin of the 71M6515H (interrupt or DIO pin polling method, see Figure 19):
a. Interrupt Method: The IRQZ pin of the 71M6515H is connected to a pin of the host processor that can generate an
interrupt for the host processor. This is the easiest method for synchronization between the 71M6515H and the host.
The CONFIG register of the 71M6515H is set up to generate an interrupt on the IRQZ pin whenever fresh data are
ready, and the interrupt service routine of the host processor reads the fresh data out of the 71M6515H.
b. DIO pin polling method: The IRQZ pin of the 71M6515H is connected to a DIO pin of the host processor. The host
processor polls the status of the DIO pin as frequently as possible or through a timer-based polling method. The
CONFIG register of the 71M6515H is set up to have the IRQZ pin to go low on every fresh data ready status, and the
timer-serviced polling of the host processor will monitor the status of the DIO pin and initiate the serial communication
when IRQZ is detected. For this method to be effective, the firmware of the host processor must maintain the timer
interrupt to be the highest priority, followed by the serial communications priority.
2) Polling the READY bit in the STATUS word of the 71M6515H (status polling method, see Figure 20).
This method requires that the host processor utilizes a timer with 1ms to 5ms resolution tied into the highest-priority
interrupt. The interrupt service routine must initiate reading the STATUS register, preferably at least every 10ms, in
order to monitor the READY bit, but the host processor must wait for the response of each status request. Otherwise,
the STATUS register read operations will be stacked in the 71M6515H resulting in multiple responses.
If a delayed response is received upon a STATUS register read, the host processor will know that the 71M6515H is
within its post-processing period, which makes it necessary hat the host waits for the response. Every time the
READY bit in the STATUS register is not set, indicating that data is not available, the host should poll again
read
command
from host
read
command
from host
6515H data
6515H data
IRQZ
post-processor
active
80ms
200ms
300ms
post-processor
active
80ms
400ms
500ms
time
Figure 19: Timing Diagram (Using IRQZ, SUM_CYCLES = 12)
The communication between the 71M6515H and the host processor can always be reset without disturbing the metering
function by utilizing the UARTCSZ and BAUDRATE pins. Configuring the BAUDRATE pin without resetting the UART buffers
is not recommended. The UART of the 71M6515H can be “reset” by pulling the UARTCSZ pin low. This will force the UART
back into the default configuration while clearing all buffers (UART buffers, UART-related buffers in the firmware).
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