71M6515H_11 Datasheet, PDF (21/60 Pages) Teridian Semiconductor Corporation – Up to 10ppmC precision ultra-stable voltage reference Digital temperature compensation

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L
M
WS
S
B
B
RX
register address
time
L
M
S
S
B
B
length
L
M
S
S
B
B
most significant
data byte
71M6515H
Energy Meter IC
DATA SHEET
JULY 2011
L
M
S
S
B
B
least significant
data byte
TX
Figure 9: UART Write Operation
UART Read Register Operation
The registers are read by sending a byte, consisting of a start register address in the seven MSBs and ‘1’ in the LSB indicating
this is a read operation. It is followed by a one byte length of bytes to read. If more bytes are asked for than the size of the
addressed register, subsequent registers will be read. The bytes are in “big-endian” order (i.e. most significant byte first). See
Figure 10.
L
M
RS
S
B
B
RX
register address
L
M
S
S
B
B
length
time
TX
L
M
S
S
B
B
most significant
data byte
L
M
S
S
B
B
least significant
data byte
Figure 10: UART Read Operation
Note: In both register read and write operations, the register address can be 0 through 127 (0x7F). The register address byte
is obtained by left-shifting the register address by one bit and setting bit 0 to 1 for read or setting bit 0 to 0 for write.
Synchronous Serial Interface (SSI)
A high speed, handshake, serial interface is available to send a contiguous block of CE data to an external data logger or
DSP. The block of data, configurable as to location and size, is sent at the beginning of each ADC multiplex cycle. The SSI
interface is enabled by the SSI_EN bit and consists of the outputs SSCLK, SSDATA, and SFR and of the SRDY input pin. The
interface is compatible with 16-bit and 32-bit processors. The operation of each pin is as follows:
SSCLK: This pin provides the serial clock. The clock can be 5MHz or 10MHz, as specified by the SSI_10M bit. The
SSI_CKGATE bit controls whether SSCLK runs continuously or is gated off when no SSI activity is occurring. If SSCLK is
gated, it will begin three cycles before SFR rises and will persist three cycles after the last data bit is output.
SSDATA: This pin provides the serial output data. SSDATA changes on the rising edge of SSCLK and outputs the contents
of a block of CE words starting with address SSI_STRT and ending with SSI_END. The words are output MSB first. SSDATA
is stable with the falling edge of SSCLK.
SFR: This pin provides the framing pulse. Although CE words are always 32 bits, the SSI interface will frame the entire data
block as a single field, as multiple 16 bit fields, or as multiple 32 bit fields. The SFR pulse is one clock cycle wide, changes
state on the rising edge of SSCLK and precedes the first bit of each field. The field size is set with SSI_FSIZE: 0-entire data
block, 1-8 bit fields, 2-16 bit fields, 3-32 bit fields. The polarity of the SFR pulse can be inverted with SSI_FPOL. The first
SFR pulse in a frame will rise on the third SSCLK clock period after MUX_SYNC (fourth SSCLK period, if SSCLK is 10MHz).
MUX_SYNC can be used to synchronize the fields arriving at the data logger or DSP.
SRDY: The SRDY input should always be tied to GND.
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