TL16PNP550A_08 Datasheet, PDF (7/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

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TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUGĆANDĆPLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B − MARCH 1995 − REVISED MARCH 1996
Terminal Functions (Continued)
TERMINAL
NAME
NO.
FN
RI
61
RTS
49
SCLK
55
SIN
6
SIO
57
SOUT
51
UARTBYPASS
7
VCC
XIN, XOUT
5, 22,
39, 56
63, 64
I/O
DESCRIPTION
I Ring indicator. RI is modem status signal. Its condition can be checked by reading bit 6 (RI) of the MSR. BIt
2 (TERI) of the MSR indicates that RI has transitioned from a low to a high level since the last read from the
MSR. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.
O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data.
RTS is set to its active level low by setting the RTS modem control register bit and is set to its inactive (high)
level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR.
In auto-RTS mode, RTS is set to its inactive level by the receiver threshold control logic.
O 3-state EEPROM clock. SCLK is a 3-state EEPROM clock output that controls address and data transfer.
A 100 µA pulldown circuit is connected to this terminal.
I Serial data. SIN is input from a connected communications device.
I/O 3-State bidirectional EEPROM serial data bus. During output mode, SIO provides only read opcode and
address which are sourced at the falling edge of SCLK. During input mode it provides the data which is
captured at the rising edge of SCLK. A 100 µA pulldown circuit is connected to this terminal.
O Composite serial data output to a connected communication device. SOUT is set to the marking (high) level
as a result of master reset.
I UART bypass. When it is active, UARTBYPASS disables the UART and the TL16PNP550A acts as a PnP
stand-alone controller.
5-V supply voltage.
I/O External clock. XIN and XOUT connect the TL16PNP550A to the main timing reference, a 22-MHz clock or
crystal.
detailed description
autoflow control
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the input must be active before the
transmitter FIFO can emit data (see Figure 1). Auto-RTS becomes active when the receiver needs more data
and notifies the sending serial device (see Figure 1). When RTS is connected to CTS, data transmission does
not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated if ACE1 and ACE2
are TL16PNP550As with enabled autoflow control. If autoflow control is not enabled, overrun errors occur when
the transmit data rate exceeds the receiver FIFO read latency.
ACE1
ACE2
D7 −D0
RCV
FIFO
XMT
FIFO
Serial to
Parallel
Flow
Control
SIN
RTS
Parallel
to Serial
SOUT
Flow
Control
CTS
SOUT
Parallel
to Serial
CTS
Flow
Control
SIN
RTS
Serial to
Parallel
Flow
Control
XMT
FIFO
RCV
FIFO
D7 −D0
Figure 1. Autoflow Control Example (Auto-RTS and Auto-CTS)
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