TL16PNP550A_08 Datasheet, PDF (38/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

TL16PNP550A
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ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUGĆANDĆPLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B − MARCH 1995 − REVISED MARCH 1996
PRINCIPLES OF OPERATION
receiver buffer register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16 × receiver clock (RCLK). Receiver section control is a function of the ACE
line control register.
The ACE RSR receives serial data from the serial input (SIN) terminal. The RSR then deserializes the data and
moves it into the RBR FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received
data available interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data is read out
of the RBR. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control
register.
scratch register
The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense
that it temporarily holds the programmer’s data without affecting any other ACE operation.
transmitter holding register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is supplied by the baud out (BAUDOUT) clock signal. Transmitter section control is a
function of the ACE line control register.
The ACE THR receives data off the internal data bus and when the TSR is idle, moves the data into the TSR.
The TSR serializes the data and outputs it at the serial output (SOUT). In the TL16C450 mode, if the THR is
empty and the transmitter holding register empty (THRE) interrupt is enabled, an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.
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