TL16PNP550A_08 Datasheet, PDF (12/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

TL16PNP550A
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ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUGĆANDĆPLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B − MARCH 1995 − REVISED MARCH 1996
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 5)
PARAMETER
ALTERNATE
SYMBOL
FIGURE
TEST CONDITIONS
MIN MAX UNIT
td10
Delay time, stop (SIN) to set INTRPT or read
RBR to LSI interrupt (IRQx)
tSINT
Figure 9,
Figure 10,
Figure 11
1
RCLK
cycle
td11
Delay time, read RBR/LSR (IOR) to reset
INTRPT (IRQx)
tRINT
Figure 9,
Figure 10,
Figure 11
CL = 75 pF
70 ns
NOTE 5: In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt identification
register or line status register).
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Figure 12)
PARAMETER
td12 Delay time, initial write (IRQx) to transmit start (SOUT)
ALTERNATE
SYMBOL
tIRS
TEST CONDITIONS
td13 Delay time, start (SOUT) to INTRPT (IRQx)
tSTI
td14 Delay time, IOW (WR THR) to reset INTRPT (IRQx)
tHR
td15 Delay time, initial write (IOW) to INTRPT (THRE†) (IRQx)
tSI
Delay time, read IIR† (IOR) to reset INTRPT (THRE†)
td16 _(IRQx)
tIR
† _{THRE = transmitter holding register empty; IIR = interrupt identification register.}
CL = 75 pF
CL = 75 pF
MIN MAX UNIT
8
26
baudout
cycles
8
10
baudout
cycles
50 ns
16
34
baudout
cycles
35 ns
modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, C_L = 75 pF
PARAMETER
ALTERNATE
SYMBOL
FIGURE
MIN MAX UNIT
td17
Delay time, WR MCR (IOW) to output (RTS, DTS)
td18
Delay time, modem interrupt (CTS, DSR, DCD/RI) to set INTRPT
(IRQx)
tMDO
tSIM
Figure 13
Figure 13
50 ns
35 ns
td19
Delay time, RD MSR (IOR) to reset INTRPT (IRQx)
td20
Delay time, CTS low to SOUT↓
tRIM
Figure 13
Figure 14
40 ns
24
baudout
cycles
td21
Delay time, receiver threshold byte (SIN) to RTS↑
Figure 15
3
baudout
cycles
td22
Delay time, read of last byte in receiver FIFO (IOR) to RTS↓
Figure 15
3
baudout
cycles
td23
Delay time, first data bit of 16th character (SIN) to RTS↑
Figure 16
3
baudout
cycles
td24
Delay time, RD RBR (IOR) ↓ to RTS↓
Figure 16
3
baudout
cycles
12
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