TL16PNP550A_08 Datasheet, PDF (29/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

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TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUGĆANDĆPLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B − MARCH 1995 − REVISED MARCH 1996
PRINCIPLES OF OPERATION
FIFO control register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
the FIFOs, clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signaling.
D Bit 0: FCR0, when set, enables the transmit and receive FIFOs. This bit must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
D Bit 1: FCR1, when set, clears all bytes in the receiver FIFO and resets its counter. The shift register is not
cleared. The logic 1 that is written to this bit position is self clearing.
D Bit 2: FCR2, when set, clears all bytes in the transmit FIFO and resets its counter. The shift register is not
cleared. The logic 1 that is written to this bit position is self clearing.
D Bits 3, 4, and 5: FCR3, FCR4, and FCR5 are reserved for future use.
D Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 14).
Table 14. Receiver FIFO Trigger Level
BIT 7
0
0
1
1
BIT 6
0
1
0
1
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
01
04
08
14
FIFO interrupt mode operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), receiver interrupt
occur as follows:
1. When the receiver FIFO reaches its programmed trigger level, the received data available interrupt is
issued to the microprocessor and IIR (3−0) are set to the value 6 (to indicate received data available).
The received data available interrupt is cleared and IIR (3−0) are set (no interrupt) when the FIFO drops
below its programmed trigger level.
2. The data ready bit (LSR0) is set as soon as a character is transferred from the shift register to the
receiver FIFO. It is cleared when the FIFO is empty.
3. The receiver line status interrupt (IIR = 0110h) has higher priority than the received data available
(IIR = 0100h) interrupt.
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