TL16PNP550A_08 Datasheet, PDF (35/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

ą
TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUGĆANDĆPLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B − MARCH 1995 − REVISED MARCH 1996
PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
D Bit 4: Bit 4 provides a local loop back feature for diagnostic testing of the ACE. When this bit is set, the
following occurs:
− The transmitter serial output (SOUT) is asserted high.
− The receiver serial input (SIN) is disconnected.
− The output of the TSR is looped back into the receiver shift register input.
− The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
− The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
− The four modem control outputs are forced to their inactive (high) states.
NOTE
OUT1 is a user-designated output signal for TL16C550. It is an internal signal and not used in the
TL16PNP550A.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the
transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational. The
modem control interrupts are also operational, but the modem control interrupt sources are now the lower four
bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the IER.
The ACE flow can be configured by programming bits 1 and 5 of the MCR. Table 18 shows that autoflow control
can be enabled by setting MCR bit 5, autoflow enable (AFE) and also setting MCR bit 1, RTS. autoflow
incorporates both auto-RTS and auto-CTS. If only auto-CTS is desired, set bit 5 and clear bit 1. If neither
auto-RTS nor auto-CTS is desired, clear bit 5.
MCR BIT 5
(AFE)
1
1
0
Table 18. ACE Flow Configuration
MCR BIT 1
(RTS)
1
0
X
ACE FLOW CONFIGURATION
Auto-RTS and auto-CTS enabled (autoflow control enabled)
Auto-CTS only enabled
Auto-RTS and auto-CTS disabled
modem status register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 13 and are
described in the following bulleted list.
D Bit 0: Bit 0 is the change in the clear-to-send (∆ CTS) indicator. This bit indicates that the CTS input has
changed state since the last time it was read by the CPU . When this bit is set (autoflow control is not enabled
and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control
is enabled, no interrupt is generated.
D Bit 1: Bit 1 is the change in the data set ready (∆ DSR) indicator. This bit indicates that the DSR input has
changed state since the last time it was read by the CPU. When this bit is set and the modem status interrupt
is enabled, a modem status interrupt is generated.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
35