TL16PNP550A_08 Datasheet, PDF (6/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

TL16PNP550A
ą
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUGĆANDĆPLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B − MARCH 1995 − REVISED MARCH 1996
Terminal Functions
TERMINAL
NAME
NO.
FN
A0 −A6
A7 −A11
32 −38
40 −44
ACONFIG0,
ACONFIG1
AEN
CS
67, 68
46
54
CS
30
CTS
60
D0 −D3
D4 −D7
DCD
10 −13
15 −18
59
DSR
62
DTR
50
EEPROM
58
EXINTR
47
GND
ICONFIG0 −
ICONFIG3
IOR
IOW
IRQ3 −IRQ4
IRQ5 −IRQ7
IRQ9 −IRQ12
IRQ15
14, 31,
48, 65
1−4
8
9
20 −21
23 −25
26 −29
19
PNPBYPASS
66
PNPS1 −
PNPS0
RESETDRV
52 −53
45
I/O
DESCRIPTION
I 12-bit ISA address terminals. All 12 bits are used during PnP autoconfiguration sequence. After
autoconfiguration, bits A0 −A2 select the ACE registers and bits A3 −A9 are used in the address decoding
to generate chip select for the device.
I Address configure. In PnP bypass mode, both ACONFIG0 and ACONFIG1 configure the COM port base
address.
I Address enable. AEN disables the ACE and PnP controller during DMA.
O Chip select. CS is a 3-state output. It controls the activity of the EEPROM. A 100 µA pulldown circuit is
connected to this terminal.
O Chip select. CS is the I/O chip select for the logical device.
I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the
modem status register (MSR). Bit 0 (∆CTS) of the modem status register indicates that this signal has
changed states since the last read from the MSR. When the modem status interrupt is enabled when CTS
changes states and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the
auto-CTS mode to control the transmitter.
I/O Data bus. D0 − D7 are eight data lines with 3-state outputs that provide a bidirectional path for data, control,
and status information between the ACE and the CPU. The output drive sinks 24 mA at 0.4 V and sources
12 mA at 2.4 V.
I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of
the MSR. Bit 3 (∆DCD) of the MSR indicates that this signal has changed levels since the last read from the
MSR. When the modem status interrupt is enabled when DCD changes states, an interrupt is generated.
I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the
MSR. Bit 1 (∆DSR) of the MSR indicates this signal has changed states since the last read from the MSR.
If the modem status interrupt is enabled when the DSR changes states, an interrupt is generated.
O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR is placed in its active level by setting the DTR bit of the MCR. DTR is placed in its
inactive level either as a result of a master reset, during loop mode operation, or clearing the DTR bit.
I/O EEPROM access. EEPROM is a 3-state bidirectional signal. When it is pulled low, either the TL16PNP550A
or controller is accessing the EEPROM. A 100 µA pullup circuit is connected to this terminal.
I External interrupt. During UARTBYPASS mode, the external logical device interrupt (EXINTR) is mapped
to the configured IRQs.
Ground (0 V). These four GND terminals must be tied to ground for proper operation.
I IRQ configure. In PnP bypass mode, ICONFIG0 , ICONFIG2, and ICONFIG3 configure the required IRQ.
I Read input. When IOR is active while the ACE is selected, the CPU is allowed to read from the ACE.
I Write input. When IOW is active while the ACE is selected, the CPU is allowed to write to the ACE.
O 3-state interrupt requests. When active (high), IRQx informs the CPU that the ACE has an interrupt to be
serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data is available
or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt.
IRQx is generated when one or all of the above conditions occur and the value of bits 0 −3 in the interrupt
request level (0 × 70) is equal to x (of IRQx). The output drive sinks 24 mA at 0.4 V and sources 12 mA at
2.4 V.
I Bypass PnP configuration sequence. When PNPBYPASS is tied to GND, the PnP autoconfiguration
sequence is bypassed.
O PnP internal states. See the PNPS1 and PNPS0 truth table in the PnP states section of this document.
I Reset. When active (high), RESETDRV clears most ACE registers and puts the ACE in wait for key state.
The CSN is reset to 0 × 00. All configuration registers are set to their power-up values.
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