TL16PNP550A_08 Datasheet, PDF (27/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

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TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUGĆANDĆPLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B − MARCH 1995 − REVISED MARCH 1996
PRINCIPLES OF OPERATION
Table 11. ACE Register Selection
DLAB† A2
A1
A0
REGISTER
0
L
L
L Receiver buffer (read), transmitter holding register (write)
0
L
L
H Interrupt enable
X
L
H
L Interrupt identification (read only)
X
L
H
L FIFO control (write)
X
L
H
H Line control
X
H
L
L Modem control
X
H
L
H Line status
X
H
H
L Modem status
X
H
H
H Scratch
1
L
L
L Divisor latch (LSB)
1
L
L
H Divisor latch (MSB)
† _{The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal}
is controlled by writing to this bit location (see Table 13).
Table 12. ACE Reset Functions
REGISTER/SIGNAL
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
SOUT
INTRPT (receiver error flag)
INTRPT (received data available)
INTRPT (transmitter holding register empty)
INTRPT (modem status changes)
RTS
DTR
Scratch Register
Divisor Latch (LSB and MSB) Registers
Receiver Buffer Registers
Transmitter Holding Register
Receiver FIFO
XMIT FIFO
RESET
CONTROL
RESET STATE
Master Reset
All bits cleared (0 −3 forced and 4 −7 permanent)
Master Reset
Bit 0 is set, bits 1 −3, 6, 7 are cleared, and bits 4 −5 are
permanently cleared
Master Reset
All bits cleared
Master Reset
All bits cleared
Master Reset
All bits cleared (6 −7 permanent)
Master Reset
Bits 5 and 6 are set, all other bits are cleared
Master Reset
Bits 0 −3 are cleared, bits 4 −7 are input signals
Master Reset
High
Read LSR/MR
Low
Read RBR/MR
Low
Read IR/Write THR/MR Low
Read MSR/MR
Low
Master Reset
High
Master Reset
High
Master Reset
No effect
Master Reset
No effect
Master Reset
No effect
Master Reset
No effect
MR/FCR1 −FCR0/
∆FCR0
All bits cleared
MR/FCR2 −FCR0/
∆FCR0
All bits cleared
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