TL16PNP550A_08 Datasheet, PDF (34/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

TL16PNP550A
ą
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUGĆANDĆPLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B − MARCH 1995 − REVISED MARCH 1996
PRINCIPLES OF OPERATION
line status register (LSR) (continued)^†
D Bit 3^‡: Bit 3 is the framing error (FE) indicator. When this bit is set, it indicates that the received character
did not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.
In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This
error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to
resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the
next start bit. The ACE samples this start bit twice and then accepts the input data.
D Bit 4^‡: Bit 4 is the break interrupt (BI) indicator. When this bit is set, it indicates that the received data input
was held in the low state for longer than a full-word transmission time. A full-word transmission time is
defined as the total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads
the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to
which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.
When a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled
after SIN goes to the marking state and receives the next valid start bit.
D Bit 5: Bit 5 is the transmitter holding register empty (THRE) indicator. This bit is set when the THR is empty,
indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when the THRE
bit is set, an interrupt is generated. THRE is set when the contents of the THR are transferred to the TSR.
This bit is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, this bit is set when
the transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO.
D Bit 6: Bit 6 is the transmitter empty (TEMT) indicator. This bit is set when the THR and the TSR are both
empty. When either the THR or the TSR contains a data character, the TEMT bit is cleared. In the FIFO
mode, this bit is set when the transmitter FIFO and shift register are both empty.
D Bit 7: In the TL16C550C mode, this bit is always cleared. In the TL16C450 mode, this bit is always cleared.
In the FIFO mode, LSR7 is set when there is at least one parity error, framing error, or break error in the
FIFO. It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.
modem control register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 13 and are described in the following
bulleted list.
D Bit 0: Bit 0 (DTR) controls the data terminal ready (DTR) output. Setting this bit forces the DTR output to
its low state. When bit 0 is cleared, DTR goes high.
D Bit 1: Bit 1 (RTS) controls the request-to-send (RTS) output in a manner identical to bit 0’s control over the
DTR output.
D Bit 2: Bit 2 (OUT1) controls the internal signal OUT1.
D Bit 3: Bit 3 (OUT2) when set in PNPBYPASS mode, the selected interrupt line IRQx is enabled; otherwise,
IRQx is 3-state.
† _{The line status register is intended for read operations only; writing to this register is not recommended outside a factory testing environment.}
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