TL16PNP550A_08 Datasheet, PDF (23/40 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

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TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUGĆANDĆPLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B − MARCH 1995 − REVISED MARCH 1996
PRINCIPLES OF OPERATION
PnP terminal states
Terminals PNPS1 and PNPS0 reflect the states of PnP logic when PNPBYPASS is set (see Table 8).
Table 8. PNPx Terminal States
PNPS1
0
0
1
1
PNPS0
0
1
0
1
PnP STATE
WAIT FOR KEY
SLEEP
ISOLATION
CONFIGURATION
If the device leaves the wait-for-key state, it means the device is in configuration mode.
Please note, when PNPBYPASS = 0, BAUDOUT is monitored using PNPS1 and RXRDY is monitored using
PNPS0.
EEPROM
The TL16PNP550A has been designed to interface with the ST93C56/66 EEPROM (SGS-Thomson) or
equivalent. The EEPROM provides the clock prescalar divisor and PnP resource data.
memory organization
The EEPROM should be organized as 128/255 words times 16 bits, so its ORG terminal should be connected
to V_CC or left unconnected. The EEPROM memory organization is shown in Table 9.
Table 9. EEPROM Memory Organization
EEPROM
BIT LOCATION
LOCATION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X 000
PnP Resource Data
X 128/255
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